SPARC: Move tlb state into the tlb.

Each "strand" may need to have a private copy of this state, but I couldn't
find anywhere in the spec that said that after looking briefly.
This prevents writes to the thread context in o3 which was causing the
pipeline to be flushed and stopping any forward progress. The other ASI
accessible state will probably need to be accessed differently if/when we get
O3 full system up and running.

--HG--
extra : convert_revision : fa7fba812d7f76564ef4a23818e60f536710d557

1 files changed, 0 insertions, 38 deletions

diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 867f959e1..3e17779a9 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -100,25 +100,6 @@ namespace SparcISA
         MISCREG_MMU_PART_ID,
         MISCREG_MMU_LSU_CTRL,
 
-        MISCREG_MMU_ITLB_C0_TSB_PS0,
-        MISCREG_MMU_ITLB_C0_TSB_PS1,
-        MISCREG_MMU_ITLB_C0_CONFIG,
-        MISCREG_MMU_ITLB_CX_TSB_PS0,
-        MISCREG_MMU_ITLB_CX_TSB_PS1,
-        MISCREG_MMU_ITLB_CX_CONFIG,
-        MISCREG_MMU_ITLB_SFSR,
-        MISCREG_MMU_ITLB_TAG_ACCESS, /* 50 */
-
-        MISCREG_MMU_DTLB_C0_TSB_PS0,
-        MISCREG_MMU_DTLB_C0_TSB_PS1,
-        MISCREG_MMU_DTLB_C0_CONFIG,
-        MISCREG_MMU_DTLB_CX_TSB_PS0,
-        MISCREG_MMU_DTLB_CX_TSB_PS1,
-        MISCREG_MMU_DTLB_CX_CONFIG,
-        MISCREG_MMU_DTLB_SFSR,
-        MISCREG_MMU_DTLB_SFAR,
-        MISCREG_MMU_DTLB_TAG_ACCESS,
-
         /** Scratchpad regiscers **/
         MISCREG_SCRATCHPAD_R0, /* 60 */
         MISCREG_SCRATCHPAD_R1,
@@ -241,25 +222,6 @@ namespace SparcISA
         uint16_t partId;
         uint64_t lsuCtrlReg;
 
-        uint64_t iTlbC0TsbPs0;
-        uint64_t iTlbC0TsbPs1;
-        uint64_t iTlbC0Config;
-        uint64_t iTlbCXTsbPs0;
-        uint64_t iTlbCXTsbPs1;
-        uint64_t iTlbCXConfig;
-        uint64_t iTlbSfsr;
-        uint64_t iTlbTagAccess;
-
-        uint64_t dTlbC0TsbPs0;
-        uint64_t dTlbC0TsbPs1;
-        uint64_t dTlbC0Config;
-        uint64_t dTlbCXTsbPs0;
-        uint64_t dTlbCXTsbPs1;
-        uint64_t dTlbCXConfig;
-        uint64_t dTlbSfsr;
-        uint64_t dTlbSfar;
-        uint64_t dTlbTagAccess;
-
         uint64_t scratchPad[8];
 
         uint64_t cpu_mondo_head;