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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 21:51:44 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 21:51:44 -0500 |
commit | 87fb0eb8de8bf66dfae5fc2d069cd17f420fc163 (patch) | |
tree | c7e3f1c653202f9d920eb740bb6dffa5ebd8df5e /src/arch/sparc/miscregfile.hh | |
parent | 2f7a4e1d1b4ab44c5a1d97eaae6ff89fd100a0a9 (diff) | |
download | gem5-87fb0eb8de8bf66dfae5fc2d069cd17f420fc163.tar.xz |
I missed a couple of WithEffects, this should do it
--HG--
extra : convert_revision : 19fce78a19b27b7ccb5e3653a64b46e6d5292915
Diffstat (limited to 'src/arch/sparc/miscregfile.hh')
-rw-r--r-- | src/arch/sparc/miscregfile.hh | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index cb46eb2aa..6063c21c8 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -257,9 +257,8 @@ namespace SparcISA // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu #if FULL_SYSTEM - void setFSRegWithEffect(int miscReg, const MiscReg &val, - ThreadContext *tc); - MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc); + void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); + MiscReg readFSReg(int miscReg, ThreadContext * tc); // Update interrupt state on softint or pil change void checkSoftInt(ThreadContext *tc); |