Fix up instructions to read and write control registers, and got rid of the control register fields which won't work on a big endian host.

--HG--
extra : convert_revision : 1b518873b6e1a073b58cbe27642537d5ae3a604d

1 files changed, 21 insertions, 201 deletions

diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 6d624787d..f74943256 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -92,8 +92,7 @@ namespace SparcISA
         MISCREG_HSTICK_CMPR,
 
         /** Floating Point Status Register */
-        MISCREG_FSR,
-        NumMiscRegs
+        MISCREG_FSR
     };
 
     // The control registers, broken out into fields
@@ -102,93 +101,16 @@ namespace SparcISA
       private:
 
         /* ASR Registers */
-        union {
-            uint64_t y;		// Y (used in obsolete multiplication)
-            struct {
-                uint64_t value:32;	// The actual value stored in y
-                uint64_t :32;	// reserved bits
-            } yFields;
-        };
-        union {
-            uint8_t	ccr;		// Condition Code Register
-            struct {
-                union {
-                    uint8_t icc:4;	// 32-bit condition codes
-                    struct {
-                        uint8_t c:1;	// Carry
-                        uint8_t v:1;	// Overflow
-                        uint8_t z:1;	// Zero
-                        uint8_t n:1;	// Negative
-                    } iccFields;
-                };
-                union {
-                    uint8_t xcc:4;	// 64-bit condition codes
-                    struct {
-                        uint8_t c:1;	// Carry
-                        uint8_t v:1;	// Overflow
-                        uint8_t z:1;	// Zero
-                        uint8_t n:1;	// Negative
-                    } xccFields;
-                };
-            } ccrFields;
-        };
+        uint64_t y;		// Y (used in obsolete multiplication)
+        uint8_t	ccr;		// Condition Code Register
         uint8_t asi;		// Address Space Identifier
-        union {
-            uint64_t tick;		// Hardware clock-tick counter
-            struct {
-                int64_t counter:63;	// Clock-tick count
-                uint64_t npt:1;		// Non-priveleged trap
-            } tickFields;
-        };
-        union {
-            uint8_t		fprs;	// Floating-Point Register State
-            struct {
-                uint8_t dl:1;		// Dirty lower
-                uint8_t du:1;		// Dirty upper
-                uint8_t fef:1;		// FPRS enable floating-Point
-            } fprsFields;
-        };
-        union {
-            uint64_t gsr;		//General Status Register
-            struct {
-                uint64_t mask:32;
-                uint64_t :4;
-                uint64_t im:1;
-                uint64_t irnd:2;
-                uint64_t :17;
-                uint64_t scale:5;
-                uint64_t align:3;
-            } gsrFields;
-        };
-        union {
-            uint64_t softint;
-            struct {
-                uint64_t tm:1;
-                uint64_t int_level:14;
-                uint64_t sm:1;
-            } softintFields;
-        };
-        union {
-            uint64_t tick_cmpr;		// Hardware tick compare registers
-            struct {
-                uint64_t tick_cmpr:63;	// Clock-tick count
-                uint64_t int_dis:1;		// Non-priveleged trap
-            } tick_cmprFields;
-        };
-        union {
-            uint64_t stick;		// Hardware clock-tick counter
-            struct {
-                int64_t :63;	// Not used, storage in SparcSystem
-                uint64_t npt:1;		// Non-priveleged trap
-            } stickFields;
-        };
-        union {
-            uint64_t stick_cmpr;		// Hardware tick compare registers
-            struct {
-                uint64_t tick_cmpr:63;	// Clock-tick count
-                uint64_t int_dis:1;		// Non-priveleged trap
-            } stick_cmprFields;
-        };
+        uint64_t tick;		// Hardware clock-tick counter
+        uint8_t	fprs;		// Floating-Point Register State
+        uint64_t gsr;		// General Status Register
+        uint64_t softint;
+        uint64_t tick_cmpr;	// Hardware tick compare registers
+        uint64_t stick;		// Hardware clock-tick counter
+        uint64_t stick_cmpr;	// Hardware tick compare registers
 
 
         /* Privileged Registers */
@@ -196,37 +118,12 @@ namespace SparcISA
                                 // previous trap level)
         uint64_t tnpc[MaxTL];	// Trap Next Program Counter (value from
                                 // previous trap level)
-        union {
-            uint64_t tstate[MaxTL];	// Trap State
-            struct {
-                //Values are from previous trap level
-                uint64_t cwp:5;		// Current Window Pointer
-                uint64_t :3;	// Reserved bits
-                uint64_t pstate:13;	// Process State
-                uint64_t :3;	// Reserved bits
-                uint64_t asi:8;		// Address Space Identifier
-                uint64_t ccr:8;		// Condition Code Register
-                uint64_t gl:8;		// Global level
-            } tstateFields[MaxTL];
-        };
+        uint64_t tstate[MaxTL];	// Trap State
         uint16_t tt[MaxTL];	// Trap Type (Type of trap which occured
                                 // on the previous level)
         uint64_t tba;		// Trap Base Address
 
-        union {
-            uint16_t pstate;		// Process State Register
-            struct {
-                uint16_t :1;		// reserved
-                uint16_t ie:1;		// Interrupt enable
-                uint16_t priv:1;	// Privelege mode
-                uint16_t am:1;		// Address mask
-                uint16_t pef:1;		// PSTATE enable floating-point
-                uint16_t :1;		// reserved2
-                uint16_t mm:2;		// Memory Model
-                uint16_t tle:1;		// Trap little-endian
-                uint16_t cle:1;		// Current little-endian
-            } pstateFields;
-        };
+        uint16_t pstate;	// Process State Register
         uint8_t tl;		// Trap Level
         uint8_t pil;		// Process Interrupt Register
         uint8_t cwp;		// Current Window Pointer
@@ -234,97 +131,20 @@ namespace SparcISA
         uint8_t canrestore;	// Restorable windows
         uint8_t cleanwin;	// Clean windows
         uint8_t otherwin;	// Other windows
-        union {
-            uint8_t wstate;		// Window State
-            struct {
-                uint8_t normal:3;	// Bits TT<4:2> are set to on a normal
-                                        // register window trap
-                uint8_t other:3;	// Bits TT<4:2> are set to on an "otherwin"
-                                        // register window trap
-            } wstateFields;
-        };
+        uint8_t wstate;		// Window State
         uint8_t gl;             // Global level register
 
-
         /** Hyperprivileged Registers */
-        union {
-            uint64_t hpstate; // Hyperprivileged State Register
-            struct {
-                uint8_t tlz: 1;
-                uint8_t :1;
-                uint8_t hpriv:1;
-                uint8_t :2;
-                uint8_t red:1;
-                uint8_t :4;
-                uint8_t ibe:1;
-                uint8_t id:1;
-            } hpstateFields;
-        };
-
-        uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
+        uint64_t hpstate;	// Hyperprivileged State Register
+        uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
         uint64_t hintp;
-        uint64_t htba; // Hyperprivileged Trap Base Address register
-        union {
-            uint64_t hstick_cmpr;		// Hardware tick compare registers
-            struct {
-                uint64_t tick_cmpr:63;	// Clock-tick count
-                uint64_t int_dis:1;		// Non-priveleged trap
-            } hstick_cmprFields;
-        };
-
-        uint64_t strandStatusReg; // Per strand status register
+        uint64_t htba;		// Hyperprivileged Trap Base Address register
+        uint64_t hstick_cmpr;	// Hardware tick compare registers
 
+        uint64_t strandStatusReg;// Per strand status register
 
         /** Floating point misc registers. */
-        union {
-            uint64_t	fsr;	// Floating-Point State Register
-            struct {
-                union {
-                    uint64_t cexc:5;	// Current excpetion
-                    struct {
-                        uint64_t nxc:1;		// Inexact
-                        uint64_t dzc:1;		// Divide by zero
-                        uint64_t ufc:1;		// Underflow
-                        uint64_t ofc:1;		// Overflow
-                        uint64_t nvc:1;		// Invalid operand
-                    } cexcFields;
-                };
-                union {
-                    uint64_t aexc:5;		// Accrued exception
-                    struct {
-                        uint64_t nxc:1;		// Inexact
-                        uint64_t dzc:1;		// Divide by zero
-                        uint64_t ufc:1;		// Underflow
-                        uint64_t ofc:1;		// Overflow
-                        uint64_t nvc:1;		// Invalid operand
-                    } aexcFields;
-                };
-                uint64_t fcc0:2;		// Floating-Point condtion codes
-                uint64_t :1;		// Reserved bits
-                uint64_t qne:1;			// Deferred trap queue not empty
-                                                // with no queue, it should read 0
-                uint64_t ftt:3;			// Floating-Point trap type
-                uint64_t ver:3;			// Version (of the FPU)
-                uint64_t :2;		// Reserved bits
-                uint64_t ns:1;			// Nonstandard floating point
-                union {
-                    uint64_t tem:5;			// Trap Enable Mask
-                    struct {
-                        uint64_t nxm:1;		// Inexact
-                        uint64_t dzm:1;		// Divide by zero
-                        uint64_t ufm:1;		// Underflow
-                        uint64_t ofm:1;		// Overflow
-                        uint64_t nvm:1;		// Invalid operand
-                    } temFields;
-                };
-                uint64_t :2;		// Reserved bits
-                uint64_t rd:2;			// Rounding direction
-                uint64_t fcc1:2;		// Floating-Point condition codes
-                uint64_t fcc2:2;		// Floating-Point condition codes
-                uint64_t fcc3:2;		// Floating-Point condition codes
-                uint64_t :26;		// Reserved bits
-            } fsrFields;
-        };
+        uint64_t fsr;		// Floating-Point State Register
 
         ASI implicitInstAsi;
         ASI implicitDataAsi;
@@ -386,8 +206,8 @@ namespace SparcISA
 
       protected:
 
-        bool isHyperPriv() { return hpstateFields.hpriv; }
-        bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
+        bool isHyperPriv() { return (hpstate & (1 << 2)); }
+        bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
         bool isNonPriv() { return !isPriv(); }
         inline void setImplicitAsis();
     };