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author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
commit | 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 (patch) | |
tree | 736bc7ea34184fb103fd836e67672521193602a7 /src/arch/sparc/miscregfile.hh | |
parent | f3ba6d20f6070c30418866e627e2418f39b433dd (diff) | |
download | gem5-2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0.tar.xz |
Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
Diffstat (limited to 'src/arch/sparc/miscregfile.hh')
-rw-r--r-- | src/arch/sparc/miscregfile.hh | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index 771cb1ed6..ac1ad90b9 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -32,9 +32,11 @@ #ifndef __ARCH_SPARC_MISCREGFILE_HH__ #define __ARCH_SPARC_MISCREGFILE_HH__ +#include "arch/sparc/asi.hh" #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" #include "arch/sparc/types.hh" +#include "cpu/cpuevent.hh" #include <string> @@ -329,6 +331,9 @@ namespace SparcISA } fsrFields; }; + ASI implicitInstAsi; + ASI implicitDataAsi; + // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu #if FULL_SYSTEM @@ -374,6 +379,16 @@ namespace SparcISA void setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc); + ASI getInstAsid() + { + return implicitInstAsi; + } + + ASI getDataAsid() + { + return implicitDataAsi; + } + void serialize(std::ostream & os); void unserialize(Checkpoint * cp, const std::string & section); @@ -385,6 +400,7 @@ namespace SparcISA bool isHyperPriv() { return hpstateFields.hpriv; } bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; } bool isNonPriv() { return !isPriv(); } + inline void setImplicitAsis(); }; } |