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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-10-10 00:31:51 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-10-10 00:31:51 -0700 |
| commit | 8eec565d0ddeb6a788bc084180b223757fd9d05f (patch) | |
| tree | c97294ac68ae6ff9db4ba3c7acafd94d8aed5971 /src/arch/sparc/mmapped_ipr.hh | |
| parent | 5bab52d56ddd482ae7eb1a6ae45d2a97fd457ca2 (diff) | |
| download | gem5-8eec565d0ddeb6a788bc084180b223757fd9d05f.tar.xz | |
SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.
Diffstat (limited to 'src/arch/sparc/mmapped_ipr.hh')
| -rw-r--r-- | src/arch/sparc/mmapped_ipr.hh | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/arch/sparc/mmapped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh index 28e3ec259..68c73cac0 100644 --- a/src/arch/sparc/mmapped_ipr.hh +++ b/src/arch/sparc/mmapped_ipr.hh @@ -48,21 +48,13 @@ namespace SparcISA inline Tick handleIprRead(ThreadContext *xc, Packet *pkt) { -#if FULL_SYSTEM return xc->getDTBPtr()->doMmuRegRead(xc, pkt); -#else - panic("Shouldn't have a memory mapped register in SE\n"); -#endif } inline Tick handleIprWrite(ThreadContext *xc, Packet *pkt) { -#if FULL_SYSTEM return xc->getDTBPtr()->doMmuRegWrite(xc, pkt); -#else - panic("Shouldn't have a memory mapped register in SE\n"); -#endif } |