arch: Add support for m5ops using mmapped IPRs

In order to support m5ops on virtualized CPUs, we need to either
intercept hypercall instructions or provide a memory mapped m5ops
interface. Since KVM does not normally pass the results of hypercalls
to userspace, which makes that method unfeasible. This changeset
introduces support for m5ops using memory mapped mmapped IPRs. This is
implemented by adding a class of "generic" IPRs which are handled by
architecture-independent code. Such IPRs always have bit 63 set and
are handled by handleGenericIprRead() and
handleGenericIprWrite(). Platform specific impementations of
handleIprRead and handleIprWrite should use
GenericISA::isGenericIprAccess to determine if an IPR address should
be handled by the generic code instead of the architecture-specific
code. Platforms that don't need their own IPR support can reuse
GenericISA::handleIprRead() and GenericISA::handleIprWrite().

1 files changed, 9 insertions, 2 deletions

diff --git a/src/arch/sparc/mmapped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh
index 153944e9d..e7d27eed5 100644
--- a/src/arch/sparc/mmapped_ipr.hh
+++ b/src/arch/sparc/mmapped_ipr.hh
@@ -37,6 +37,7 @@
  * ISA-specific helper functions for memory mapped IPR accesses.
  */
 
+#include "arch/generic/mmapped_ipr.hh"
 #include "arch/sparc/tlb.hh"
 #include "cpu/thread_context.hh"
 #include "mem/packet.hh"
@@ -47,13 +48,19 @@ namespace SparcISA
 inline Cycles
 handleIprRead(ThreadContext *xc, Packet *pkt)
 {
-    return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
+    if (GenericISA::isGenericIprAccess(pkt))
+        return GenericISA::handleGenericIprRead(xc, pkt);
+    else
+        return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
 }
 
 inline Cycles
 handleIprWrite(ThreadContext *xc, Packet *pkt)
 {
-    return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
+    if (GenericISA::isGenericIprAccess(pkt))
+        return GenericISA::handleGenericIprWrite(xc, pkt);
+    else
+        return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
 }