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author | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
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committer | Alexandru Dutu <alexandru.dutu@amd.com> | 2014-11-23 18:01:09 -0800 |
commit | 1f539f13c32ad5a9187d56a098d4c857639b0e05 (patch) | |
tree | 7618c3b946d9c25d9b22018f226eee77b6de4aaf /src/arch/sparc/pagetable.hh | |
parent | c11bcb8119273ef91c40a25b8fd9471a887d0ee5 (diff) | |
download | gem5-1f539f13c32ad5a9187d56a098d4c857639b0e05.tar.xz |
mem: Page Table map api modification
This patch adds uncacheable/cacheable and read-only/read-write attributes to
the map method of PageTableBase. It also modifies the constructor of TlbEntry
structs for all architectures to consider the new attributes.
Diffstat (limited to 'src/arch/sparc/pagetable.hh')
-rw-r--r-- | src/arch/sparc/pagetable.hh | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh index aba17e505..727727f95 100644 --- a/src/arch/sparc/pagetable.hh +++ b/src/arch/sparc/pagetable.hh @@ -230,14 +230,18 @@ struct TlbEntry TlbEntry() {} - TlbEntry(Addr asn, Addr vaddr, Addr paddr) + TlbEntry(Addr asn, Addr vaddr, Addr paddr, + bool uncacheable, bool read_only) { uint64_t entry = 0; - entry |= 1ULL << 1; // Writable + if (!read_only) + entry |= 1ULL << 1; // Writable entry |= 0ULL << 2; // Available in nonpriveleged mode entry |= 0ULL << 3; // No side effects - entry |= 1ULL << 4; // Virtually cachable - entry |= 1ULL << 5; // Physically cachable + if (!uncacheable) { + entry |= 1ULL << 4; // Virtually cachable + entry |= 1ULL << 5; // Physically cachable + } entry |= 0ULL << 6; // Not locked entry |= mbits(paddr, 39, 13); // Physical address entry |= 0ULL << 48; // size = 8k |