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authorGabe Black <gblack@eecs.umich.edu>2007-10-25 19:04:44 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-10-25 19:04:44 -0700
commitfddfa71658a35f91c249ce0b7b67984d979a4fb4 (patch)
tree2502a148cc3da2e0ebb53bdf9027a4b5a427423e /src/arch/sparc/pagetable.hh
parent0711f4f17a4b4ac61b07cbe742f0d193f919ea8f (diff)
downloadgem5-fddfa71658a35f91c249ce0b7b67984d979a4fb4.tar.xz
TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.
--HG-- extra : convert_revision : 2421af11f62f60fb48faeee6bddadac2987df0e8
Diffstat (limited to 'src/arch/sparc/pagetable.hh')
-rw-r--r--src/arch/sparc/pagetable.hh33
1 files changed, 30 insertions, 3 deletions
diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh
index 961870579..bf7f34b60 100644
--- a/src/arch/sparc/pagetable.hh
+++ b/src/arch/sparc/pagetable.hh
@@ -190,16 +190,43 @@ struct TlbRange {
struct TlbEntry {
- Addr pageStart;
+ TlbEntry(Addr asn, Addr vaddr, Addr paddr)
+ {
+ uint64_t entry = 0;
+ entry |= 1ULL << 1; // Writable
+ entry |= 0ULL << 2; // Available in nonpriveleged mode
+ entry |= 0ULL << 3; // No side effects
+ entry |= 1ULL << 4; // Virtually cachable
+ entry |= 1ULL << 5; // Physically cachable
+ entry |= 0ULL << 6; // Not locked
+ entry |= mbits(paddr, 39, 13); // Physical address
+ entry |= 0ULL << 48; // size = 8k
+ entry |= 0uLL << 59; // Endianness not inverted
+ entry |= 0ULL << 60; // Not no fault only
+ entry |= 0ULL << 61; // size = 8k
+ entry |= 1ULL << 63; // valid
+ pte = PageTableEntry(entry);
+
+ range.va = vaddr;
+ range.size = 8*(1<<10);
+ range.contextId = asn;
+ range.partitionId = 0;
+ range.real = false;
+
+ valid = true;
+ }
TlbEntry()
{}
- TlbEntry(Addr addr) : pageStart(addr)
- {}
TlbRange range;
PageTableEntry pte;
bool used;
bool valid;
+ Addr pageStart()
+ {
+ return pte.paddr();
+ }
+
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);