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author | Gabe Black <gblack@eecs.umich.edu> | 2012-02-11 14:16:38 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2012-02-11 14:16:38 -0800 |
commit | 5b557a314f4dbde6f029b3f75c211332ac360f3a (patch) | |
tree | 8be804d79afc881903830e5281fc86b7f7d5d5dc /src/arch/sparc/process.cc | |
parent | aa513a4a99cb8dfc6b605797acbbb64a5601ab6e (diff) | |
download | gem5-5b557a314f4dbde6f029b3f75c211332ac360f3a.tar.xz |
SPARC: Make PSTATE and HPSTATE a BitUnion.
This gets rid of cryptic bits of code with lots of bit manipulation, and makes
some comments redundant.
Diffstat (limited to 'src/arch/sparc/process.cc')
-rw-r--r-- | src/arch/sparc/process.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index cc39ecf31..769f15497 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -161,7 +161,10 @@ Sparc32LiveProcess::initState() ThreadContext *tc = system->getThreadContext(contextIds[0]); // The process runs in user mode with 32 bit addresses - tc->setMiscReg(MISCREG_PSTATE, 0x0a); + PSTATE pstate = 0; + pstate.ie = 1; + pstate.am = 1; + tc->setMiscReg(MISCREG_PSTATE, pstate); argsInit(32 / 8, VMPageSize); } @@ -173,7 +176,9 @@ Sparc64LiveProcess::initState() ThreadContext *tc = system->getThreadContext(contextIds[0]); // The process runs in user mode - tc->setMiscReg(MISCREG_PSTATE, 0x02); + PSTATE pstate = 0; + pstate.ie = 1; + tc->setMiscReg(MISCREG_PSTATE, pstate); argsInit(sizeof(IntReg), VMPageSize); } @@ -533,27 +538,22 @@ SparcLiveProcess::setSyscallReturn(ThreadContext *tc, // check for error condition. SPARC syscall convention is to // indicate success/failure in reg the carry bit of the ccr // and put the return value itself in the standard return value reg (). + PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); if (return_value.successful()) { // no error, clear XCC.C tc->setIntReg(NumIntArchRegs + 2, tc->readIntReg(NumIntArchRegs + 2) & 0xEE); - // tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE); IntReg val = return_value.value(); - if (bits(tc->readMiscRegNoEffect( - SparcISA::MISCREG_PSTATE), 3, 3)) { + if (pstate.am) val = bits(val, 31, 0); - } tc->setIntReg(ReturnValueReg, val); } else { // got an error, set XCC.C tc->setIntReg(NumIntArchRegs + 2, tc->readIntReg(NumIntArchRegs + 2) | 0x11); - // tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11); IntReg val = -return_value.value(); - if (bits(tc->readMiscRegNoEffect( - SparcISA::MISCREG_PSTATE), 3, 3)) { + if (pstate.am) val = bits(val, 31, 0); - } tc->setIntReg(ReturnValueReg, val); } } |