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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
| commit | 537239b278f7b8171d2eb09ef7f99c332266c48f (patch) | |
| tree | 31984b63cc542f0a57ca96262477575ab0130c09 /src/arch/sparc/process.cc | |
| parent | f738afb865cd82487d6300259d6e87fb50660d2a (diff) | |
| download | gem5-537239b278f7b8171d2eb09ef7f99c332266c48f.tar.xz | |
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
Diffstat (limited to 'src/arch/sparc/process.cc')
| -rw-r--r-- | src/arch/sparc/process.cc | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 41a1c2136..29b1a244b 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -121,6 +121,12 @@ Sparc32LiveProcess::startup() threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0); //Set the ASI register to something fixed threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); + + /* + * T1 specific registers + */ + //Turn on the icache, dcache, dtb translation, and itb translation. + threadContexts[0]->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); } void @@ -137,7 +143,7 @@ Sparc64LiveProcess::startup() threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0); threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0); - // + /* * Register window management registers */ @@ -163,6 +169,12 @@ Sparc64LiveProcess::startup() threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0); //Set the ASI register to something fixed threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); + + /* + * T1 specific registers + */ + //Turn on the icache, dcache, dtb translation, and itb translation. + threadContexts[0]->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); } M5_32_auxv_t::M5_32_auxv_t(int32_t type, int32_t val) |