Implement PR/HPR/ASR for full system

Rip out storage in miscreg file that will never store anything
Add storage and defines for Priv and Hyperpriv registers
Change defines to match the spec register numbers
Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.
Use bitfields for things that are rarely used in decoder
Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead

Still todo:
Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs
Deal with signaling interrupts on timer expiration
Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU

Other misc:
Instruction decoding needs major help!

src/arch/sparc/isa/decoder.isa:
    Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely
    changed to bitfields.
src/arch/sparc/isa/formats/integerop.isa:
    These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set
    at once
src/arch/sparc/isa/formats/priv.isa:
    PrivTick is handled by miscreg now, don't need a seperate class for it
src/arch/sparc/isa/operands.isa:
    prune the number of control regs down to a reasonable amount
src/arch/sparc/isa_traits.hh:
    Replace 8 defines with 1 and flick some bits
src/arch/sparc/process.cc:
    Better to clean the entire registers that specific bits which leads to indetermanistic behavior.
src/arch/sparc/regfile.hh:
    Rip out storage that will never be backed by anything
    Add storage for Priv and Hyperpriv registers
    change defines to match the spec
    change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
    change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.

--HG--
extra : convert_revision : 64276a3ea884eea70112e721f85a515946ded4c2

1 files changed, 6 insertions, 15 deletions

diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 250c1bec4..fe6692cc3 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -110,22 +110,13 @@ SparcLiveProcess::startup()
     //From the SPARC ABI
 
     //The process runs in user mode
-    execContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE_PRIV, 0);
-    //Interrupts are enabled
-    execContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE_IE, 1);
-    //Round to nearest
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_RD, 0);
-    //Floating point traps are not enabled
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_TEM, 0);
-    //Turn non standard mode off
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_NS, 0);
-    //The floating point queue is empty
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_QNE, 0);
-    //There are no accrued eexecContext[0]eptions
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_AEXC, 0);
-    //There are no current eexecContext[0]eptions
-    execContexts[0]->setMiscRegWithEffect(MISCREG_FSR_CEXC, 0);
+    execContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02);
 
+    //Setup default FP state
+    execContexts[0]->setMiscReg(MISCREG_FSR, 0);
+
+    execContexts[0]->setMiscReg(MISCREG_TICK, 0);
+    //
     /*
      * Register window management registers
      */