Handle access to ASI_QUEUE

Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file

src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
    add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
    Handle access to ASI_QUEUE

--HG--
extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0

1 files changed, 86 insertions, 0 deletions

diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index 06ba13423..5d8ac6a17 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -254,6 +254,92 @@ void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 
     // FSR
     dest->setMiscReg(MISCREG_FSR, src->readMiscReg(MISCREG_FSR));
+
+    //Strand Status Register
+    dest->setMiscReg(MISCREG_STRAND_STS_REG,
+            src->readMiscReg(MISCREG_STRAND_STS_REG));
+
+    // MMU Registers
+    dest->setMiscReg(MISCREG_MMU_P_CONTEXT,
+            src->readMiscReg(MISCREG_MMU_P_CONTEXT));
+    dest->setMiscReg(MISCREG_MMU_S_CONTEXT,
+            src->readMiscReg(MISCREG_MMU_S_CONTEXT));
+    dest->setMiscReg(MISCREG_MMU_PART_ID,
+            src->readMiscReg(MISCREG_MMU_PART_ID));
+    dest->setMiscReg(MISCREG_MMU_LSU_CTRL,
+            src->readMiscReg(MISCREG_MMU_LSU_CTRL));
+
+    dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0,
+            src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0));
+    dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1,
+            src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1));
+    dest->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG,
+            src->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG));
+    dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0,
+            src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0));
+    dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1,
+            src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1));
+    dest->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG,
+            src->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
+    dest->setMiscReg(MISCREG_MMU_ITLB_SFSR,
+            src->readMiscReg(MISCREG_MMU_ITLB_SFSR));
+    dest->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS,
+            src->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS));
+
+    dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0,
+            src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0));
+    dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1,
+            src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1));
+    dest->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG,
+            src->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG));
+    dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0,
+            src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0));
+    dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1,
+            src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1));
+    dest->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG,
+            src->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
+    dest->setMiscReg(MISCREG_MMU_DTLB_SFSR,
+            src->readMiscReg(MISCREG_MMU_DTLB_SFSR));
+    dest->setMiscReg(MISCREG_MMU_DTLB_SFAR,
+            src->readMiscReg(MISCREG_MMU_DTLB_SFAR));
+    dest->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
+            src->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS));
+
+    // Scratchpad Registers
+    dest->setMiscReg(MISCREG_SCRATCHPAD_R0,
+            src->readMiscReg(MISCREG_SCRATCHPAD_R0));
+    dest->setMiscReg(MISCREG_SCRATCHPAD_R1,
+            src->readMiscReg(MISCREG_SCRATCHPAD_R1));
+    dest->setMiscReg(MISCREG_SCRATCHPAD_R2,
+            src->readMiscReg(MISCREG_SCRATCHPAD_R2));
+    dest->setMiscReg(MISCREG_SCRATCHPAD_R3,
+            src->readMiscReg(MISCREG_SCRATCHPAD_R3));
+    dest->setMiscReg(MISCREG_SCRATCHPAD_R4,
+            src->readMiscReg(MISCREG_SCRATCHPAD_R4));
+    dest->setMiscReg(MISCREG_SCRATCHPAD_R5,
+            src->readMiscReg(MISCREG_SCRATCHPAD_R5));
+    dest->setMiscReg(MISCREG_SCRATCHPAD_R6,
+            src->readMiscReg(MISCREG_SCRATCHPAD_R6));
+    dest->setMiscReg(MISCREG_SCRATCHPAD_R7,
+            src->readMiscReg(MISCREG_SCRATCHPAD_R7));
+
+    // Queue Registers
+    dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD,
+            src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD));
+    dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL,
+            src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL));
+    dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD,
+            src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD));
+    dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL,
+            src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL));
+    dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD,
+            src->readMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD));
+    dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL,
+            src->readMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL));
+    dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD,
+            src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD));
+    dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL,
+            src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL));
 }
 
 void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)