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authorGabe Black <gblack@eecs.umich.edu>2006-11-01 16:44:45 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-01 16:44:45 -0500
commit2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 (patch)
tree736bc7ea34184fb103fd836e67672521193602a7 /src/arch/sparc/regfile.cc
parentf3ba6d20f6070c30418866e627e2418f39b433dd (diff)
downloadgem5-2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0.tar.xz
Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
Diffstat (limited to 'src/arch/sparc/regfile.cc')
-rw-r--r--src/arch/sparc/regfile.cc31
1 files changed, 13 insertions, 18 deletions
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index 5eb874d39..65e6017da 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -79,24 +79,20 @@ MiscReg RegFile::readMiscReg(int miscReg)
return miscRegFile.readReg(miscReg);
}
-MiscReg RegFile::readMiscRegWithEffect(int miscReg,
- Fault &fault, ThreadContext *tc)
+MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc)
{
- fault = NoFault;
return miscRegFile.readRegWithEffect(miscReg, tc);
}
-Fault RegFile::setMiscReg(int miscReg, const MiscReg &val)
+void RegFile::setMiscReg(int miscReg, const MiscReg &val)
{
miscRegFile.setReg(miscReg, val);
- return NoFault;
}
-Fault RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
+void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
ThreadContext * tc)
{
miscRegFile.setRegWithEffect(miscReg, val, tc);
- return NoFault;
}
FloatReg RegFile::readFloatReg(int floatReg, int width)
@@ -122,27 +118,26 @@ FloatRegBits RegFile::readFloatRegBits(int floatReg)
FloatRegFile::SingleWidth);
}
-Fault RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
+void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
{
- return floatRegFile.setReg(floatReg, val, width);
+ floatRegFile.setReg(floatReg, val, width);
}
-Fault RegFile::setFloatReg(int floatReg, const FloatReg &val)
+void RegFile::setFloatReg(int floatReg, const FloatReg &val)
{
//Use the "natural" width of a single float
- return setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
+ setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
}
-Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
{
- return floatRegFile.setRegBits(floatReg, val, width);
+ floatRegFile.setRegBits(floatReg, val, width);
}
-Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
+void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
{
//Use the "natural" width of a single float
- return floatRegFile.setRegBits(floatReg, val,
- FloatRegFile::SingleWidth);
+ floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth);
}
IntReg RegFile::readIntReg(int intReg)
@@ -150,9 +145,9 @@ IntReg RegFile::readIntReg(int intReg)
return intRegFile.readReg(intReg);
}
-Fault RegFile::setIntReg(int intReg, const IntReg &val)
+void RegFile::setIntReg(int intReg, const IntReg &val)
{
- return intRegFile.setReg(intReg, val);
+ intRegFile.setReg(intReg, val);
}
void RegFile::serialize(std::ostream &os)