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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-20 23:12:32 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-20 23:12:32 -0500 |
| commit | d8eeb2e0ff3059a47a0956fbd02234bc32804290 (patch) | |
| tree | de42362204783e9dc4bf7f01ef0093d318402815 /src/arch/sparc/regfile.cc | |
| parent | 57d11578cf424f3e1c27d27d63badcdf7d52ba9d (diff) | |
| download | gem5-d8eeb2e0ff3059a47a0956fbd02234bc32804290.tar.xz | |
fix InterruptLevel code to return the correct level
(the bit positition that is set in softint)
--HG--
extra : convert_revision : ba0e1f4ec1f74aac64c3f9bb7eb1b771e17b013a
Diffstat (limited to 'src/arch/sparc/regfile.cc')
| -rw-r--r-- | src/arch/sparc/regfile.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc index 5d8ac6a17..b36133544 100644 --- a/src/arch/sparc/regfile.cc +++ b/src/arch/sparc/regfile.cc @@ -189,10 +189,10 @@ int SparcISA::InterruptLevel(uint64_t softint) if (softint & 0x10000 || softint & 0x1) return 14; - int level = 14; - while (level >= 0 && !(1 << (level + 1) & softint)) + int level = 15; + while (level > 0 && !(1 << level & softint)) level--; - if (1 << (level + 1) & softint) + if (1 << level & softint) return level; return 0; } |