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author | Gabe Black <gblack@eecs.umich.edu> | 2006-07-22 15:50:40 -0400 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-07-22 15:50:40 -0400 |
commit | 14b11a9734ede105c626fa16e23b554e61a494f7 (patch) | |
tree | 5049071df45ef00fb5ff90117f63e9e937d4c377 /src/arch/sparc/regfile.hh | |
parent | 7ccdb7accc073d282e9df804da400394a795b2ae (diff) | |
download | gem5-14b11a9734ede105c626fa16e23b554e61a494f7.tar.xz |
Fixed subtract with carry, and started some work with floating point.
src/arch/sparc/isa/decoder.isa:
fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point.
src/arch/sparc/isa/operands.isa:
Added in floating point operands, and changed the numbering of operands.
src/arch/sparc/regfile.hh:
Fixed some memory errors related to floating point.
--HG--
extra : convert_revision : fa0aef2021a5cf99f175fceeb533fe63eb5f805c
Diffstat (limited to 'src/arch/sparc/regfile.hh')
-rw-r--r-- | src/arch/sparc/regfile.hh | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index e5192d684..db48b2d78 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -180,7 +180,7 @@ namespace SparcISA //Since the floating point registers overlap each other, //A generic storage space is used. The float to be returned is //pulled from the appropriate section of this region. - char regSpace[SingleWidth / 8 * NumFloatRegs]; + char regSpace[(SingleWidth / 8) * NumFloatRegs]; public: @@ -198,15 +198,15 @@ namespace SparcISA { case SingleWidth: float32_t result32; - memcpy(&result32, regSpace + 4 * floatReg, width); + memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); return htog(result32); case DoubleWidth: float64_t result64; - memcpy(&result64, regSpace + 4 * floatReg, width); + memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); return htog(result64); case QuadWidth: float128_t result128; - memcpy(&result128, regSpace + 4 * floatReg, width); + memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128)); return htog(result128); default: panic("Attempted to read a %d bit floating point register!", width); @@ -222,15 +222,15 @@ namespace SparcISA { case SingleWidth: uint32_t result32; - memcpy(&result32, regSpace + 4 * floatReg, width); + memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32)); return htog(result32); case DoubleWidth: uint64_t result64; - memcpy(&result64, regSpace + 4 * floatReg, width); + memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64)); return htog(result64); case QuadWidth: uint64_t result128; - memcpy(&result128, regSpace + 4 * floatReg, width); + memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128)); return htog(result128); default: panic("Attempted to read a %d bit floating point register!", width); @@ -245,15 +245,16 @@ namespace SparcISA uint32_t result32; uint64_t result64; + DPRINTF(Sparc, "Setting floating point register %d\n", floatReg); switch(width) { case SingleWidth: result32 = gtoh((uint32_t)val); - memcpy(regSpace + 4 * floatReg, &result32, width); + memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); break; case DoubleWidth: result64 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result64, width); + memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); break; case QuadWidth: panic("Quad width FP not implemented."); @@ -275,11 +276,11 @@ namespace SparcISA { case SingleWidth: result32 = gtoh((uint32_t)val); - memcpy(regSpace + 4 * floatReg, &result32, width); + memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32)); break; case DoubleWidth: result64 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result64, width); + memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64)); break; case QuadWidth: panic("Quad width FP not implemented."); |