first cut at a sparc tlb

src/arch/sparc/SConscript:
    Add code to serialize/unserialze tlb entries
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    update asi names for how they're listed in the supplement
    add asis
    add more asi functions
src/arch/sparc/isa_traits.hh:
    move the interrupt stuff and some basic address space stuff into isa traits
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    add mmu registers to tlb
    get rid of implicit asi stuff... the tlb will handle it
src/arch/sparc/regfile.hh:
    make isnt/dataAsid return ints not asis
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
    first cut at sparc tlb
src/arch/sparc/vtophys.hh:
    pagatable nedes to be included here
src/mem/request.hh:
    add asi and if the request is a memory mapped register to the requset object
src/sim/host.hh:
    fix incorrect definition of LL

--HG--
extra : convert_revision : 6c85cd1681c62c8cd8eab04f70b1f15a034b0aa3

1 files changed, 2 insertions, 2 deletions

diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index 9f33435f6..0a09d0f66 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -82,12 +82,12 @@ namespace SparcISA
         void setMiscRegWithEffect(int miscReg, const MiscReg &val,
                 ThreadContext * tc);
 
-        ASI instAsid()
+        int instAsid()
         {
             return miscRegFile.getInstAsid();
         }
 
-        ASI dataAsid()
+        int dataAsid()
         {
             return miscRegFile.getDataAsid();
         }