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authorGabe Black <gblack@eecs.umich.edu>2006-11-01 16:44:45 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-01 16:44:45 -0500
commit2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 (patch)
tree736bc7ea34184fb103fd836e67672521193602a7 /src/arch/sparc/regfile.hh
parentf3ba6d20f6070c30418866e627e2418f39b433dd (diff)
downloadgem5-2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0.tar.xz
Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
Diffstat (limited to 'src/arch/sparc/regfile.hh')
-rw-r--r--src/arch/sparc/regfile.hh28
1 files changed, 18 insertions, 10 deletions
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index 500fbbba4..9f33435f6 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -32,7 +32,6 @@
#ifndef __ARCH_SPARC_REGFILE_HH__
#define __ARCH_SPARC_REGFILE_HH__
-#include "arch/sparc/faults.hh"
#include "arch/sparc/floatregfile.hh"
#include "arch/sparc/intregfile.hh"
#include "arch/sparc/isa_traits.hh"
@@ -76,14 +75,23 @@ namespace SparcISA
MiscReg readMiscReg(int miscReg);
- MiscReg readMiscRegWithEffect(int miscReg,
- Fault &fault, ThreadContext *tc);
+ MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc);
- Fault setMiscReg(int miscReg, const MiscReg &val);
+ void setMiscReg(int miscReg, const MiscReg &val);
- Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
+ void setMiscRegWithEffect(int miscReg, const MiscReg &val,
ThreadContext * tc);
+ ASI instAsid()
+ {
+ return miscRegFile.getInstAsid();
+ }
+
+ ASI dataAsid()
+ {
+ return miscRegFile.getDataAsid();
+ }
+
FloatReg readFloatReg(int floatReg, int width);
FloatReg readFloatReg(int floatReg);
@@ -92,17 +100,17 @@ namespace SparcISA
FloatRegBits readFloatRegBits(int floatReg);
- Fault setFloatReg(int floatReg, const FloatReg &val, int width);
+ void setFloatReg(int floatReg, const FloatReg &val, int width);
- Fault setFloatReg(int floatReg, const FloatReg &val);
+ void setFloatReg(int floatReg, const FloatReg &val);
- Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
+ void setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
- Fault setFloatRegBits(int floatReg, const FloatRegBits &val);
+ void setFloatRegBits(int floatReg, const FloatRegBits &val);
IntReg readIntReg(int intReg);
- Fault setIntReg(int intReg, const IntReg &val);
+ void setIntReg(int intReg, const IntReg &val);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);