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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
commit | 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (patch) | |
tree | 0868fb00a7546d90971bc18acd4f7b0bbce558c0 /src/arch/sparc/regfile.hh | |
parent | 3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (diff) | |
download | gem5-32daf6fc3fd34af0023ae74c2a1f8dd597f87242.tar.xz |
Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
Diffstat (limited to 'src/arch/sparc/regfile.hh')
-rw-r--r-- | src/arch/sparc/regfile.hh | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index 7da302eb7..2333d9da5 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -65,31 +65,11 @@ namespace SparcISA protected: IntRegFile intRegFile; // integer register file FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file public: void clear(); - MiscReg readMiscRegNoEffect(int miscReg); - - MiscReg readMiscReg(int miscReg, ThreadContext *tc); - - void setMiscRegNoEffect(int miscReg, const MiscReg &val); - - void setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc); - - int instAsid() - { - return miscRegFile.getInstAsid(); - } - - int dataAsid() - { - return miscRegFile.getDataAsid(); - } - FloatReg readFloatReg(int floatReg, int width); FloatReg readFloatReg(int floatReg); @@ -117,14 +97,6 @@ namespace SparcISA public: }; - int flattenIntIndex(ThreadContext * tc, int reg); - - static inline int - flattenFloatIndex(ThreadContext * tc, int reg) - { - return reg; - } - void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); |