New directory structure:

- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree.  See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.

SConstruct:
    Update for new directory structure.
    Modify to support build trees that are not subdirectories
    of the source tree.  See comment at top of file for
    more details.
    Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
    Update for new directory structure.

--HG--
rename : build/SConstruct => SConstruct
rename : build/default_options/ALPHA_FS => build_opts/ALPHA_FS
rename : build/default_options/ALPHA_FS_TL => build_opts/ALPHA_FS_TL
rename : build/default_options/ALPHA_SE => build_opts/ALPHA_SE
rename : build/default_options/MIPS_SE => build_opts/MIPS_SE
rename : build/default_options/SPARC_SE => build_opts/SPARC_SE
rename : Doxyfile => src/Doxyfile
rename : SConscript => src/SConscript
rename : arch/SConscript => src/arch/SConscript
rename : arch/alpha/SConscript => src/arch/alpha/SConscript
rename : arch/alpha/aout_machdep.h => src/arch/alpha/aout_machdep.h
rename : arch/alpha/arguments.cc => src/arch/alpha/arguments.cc
rename : arch/alpha/arguments.hh => src/arch/alpha/arguments.hh
rename : arch/alpha/ecoff_machdep.h => src/arch/alpha/ecoff_machdep.h
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/ev5.hh => src/arch/alpha/ev5.hh
rename : arch/alpha/faults.cc => src/arch/alpha/faults.cc
rename : arch/alpha/faults.hh => src/arch/alpha/faults.hh
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/freebsd/system.hh => src/arch/alpha/freebsd/system.hh
rename : arch/alpha/isa/branch.isa => src/arch/alpha/isa/branch.isa
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/fp.isa => src/arch/alpha/isa/fp.isa
rename : arch/alpha/isa/int.isa => src/arch/alpha/isa/int.isa
rename : arch/alpha/isa/main.isa => src/arch/alpha/isa/main.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa/opcdec.isa => src/arch/alpha/isa/opcdec.isa
rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa
rename : arch/alpha/isa/unimp.isa => src/arch/alpha/isa/unimp.isa
rename : arch/alpha/isa/unknown.isa => src/arch/alpha/isa/unknown.isa
rename : arch/alpha/isa/util.isa => src/arch/alpha/isa/util.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/aligned.hh => src/arch/alpha/linux/aligned.hh
rename : arch/alpha/linux/hwrpb.hh => src/arch/alpha/linux/hwrpb.hh
rename : arch/alpha/linux/linux.cc => src/arch/alpha/linux/linux.cc
rename : arch/alpha/linux/linux.hh => src/arch/alpha/linux/linux.hh
rename : arch/alpha/linux/process.cc => src/arch/alpha/linux/process.cc
rename : arch/alpha/linux/process.hh => src/arch/alpha/linux/process.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh
rename : arch/alpha/linux/thread_info.hh => src/arch/alpha/linux/thread_info.hh
rename : arch/alpha/linux/threadinfo.hh => src/arch/alpha/linux/threadinfo.hh
rename : arch/alpha/osfpal.cc => src/arch/alpha/osfpal.cc
rename : arch/alpha/osfpal.hh => src/arch/alpha/osfpal.hh
rename : arch/alpha/process.cc => src/arch/alpha/process.cc
rename : arch/alpha/process.hh => src/arch/alpha/process.hh
rename : arch/alpha/regfile.hh => src/arch/alpha/regfile.hh
rename : arch/alpha/stacktrace.cc => src/arch/alpha/stacktrace.cc
rename : arch/alpha/stacktrace.hh => src/arch/alpha/stacktrace.hh
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/system.hh => src/arch/alpha/system.hh
rename : arch/alpha/tlb.cc => src/arch/alpha/tlb.cc
rename : arch/alpha/tlb.hh => src/arch/alpha/tlb.hh
rename : arch/alpha/tru64/process.cc => src/arch/alpha/tru64/process.cc
rename : arch/alpha/tru64/process.hh => src/arch/alpha/tru64/process.hh
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : arch/alpha/tru64/system.hh => src/arch/alpha/tru64/system.hh
rename : arch/alpha/tru64/tru64.cc => src/arch/alpha/tru64/tru64.cc
rename : arch/alpha/tru64/tru64.hh => src/arch/alpha/tru64/tru64.hh
rename : arch/alpha/types.hh => src/arch/alpha/types.hh
rename : arch/alpha/utility.hh => src/arch/alpha/utility.hh
rename : arch/alpha/vtophys.cc => src/arch/alpha/vtophys.cc
rename : arch/alpha/vtophys.hh => src/arch/alpha/vtophys.hh
rename : arch/isa_parser.py => src/arch/isa_parser.py
rename : arch/isa_specific.hh => src/arch/isa_specific.hh
rename : arch/mips/SConscript => src/arch/mips/SConscript
rename : arch/mips/faults.cc => src/arch/mips/faults.cc
rename : arch/mips/faults.hh => src/arch/mips/faults.hh
rename : arch/mips/isa/base.isa => src/arch/mips/isa/base.isa
rename : arch/mips/isa/bitfields.isa => src/arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.isa => src/arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats/basic.isa => src/arch/mips/isa/formats/basic.isa
rename : arch/mips/isa/formats/branch.isa => src/arch/mips/isa/formats/branch.isa
rename : arch/mips/isa/formats/formats.isa => src/arch/mips/isa/formats/formats.isa
rename : arch/mips/isa/formats/fp.isa => src/arch/mips/isa/formats/fp.isa
rename : arch/mips/isa/formats/int.isa => src/arch/mips/isa/formats/int.isa
rename : arch/mips/isa/formats/mem.isa => src/arch/mips/isa/formats/mem.isa
rename : arch/mips/isa/formats/noop.isa => src/arch/mips/isa/formats/noop.isa
rename : arch/mips/isa/formats/tlbop.isa => src/arch/mips/isa/formats/tlbop.isa
rename : arch/mips/isa/formats/trap.isa => src/arch/mips/isa/formats/trap.isa
rename : arch/mips/isa/formats/unimp.isa => src/arch/mips/isa/formats/unimp.isa
rename : arch/mips/isa/formats/unknown.isa => src/arch/mips/isa/formats/unknown.isa
rename : arch/mips/isa/formats/util.isa => src/arch/mips/isa/formats/util.isa
rename : arch/mips/isa/includes.isa => src/arch/mips/isa/includes.isa
rename : arch/mips/isa/main.isa => src/arch/mips/isa/main.isa
rename : arch/mips/isa/operands.isa => src/arch/mips/isa/operands.isa
rename : arch/mips/isa_traits.cc => src/arch/mips/isa_traits.cc
rename : arch/mips/isa_traits.hh => src/arch/mips/isa_traits.hh
rename : arch/mips/linux/linux.cc => src/arch/mips/linux/linux.cc
rename : arch/mips/linux/linux.hh => src/arch/mips/linux/linux.hh
rename : arch/mips/linux/process.cc => src/arch/mips/linux/process.cc
rename : arch/mips/linux/process.hh => src/arch/mips/linux/process.hh
rename : arch/mips/process.cc => src/arch/mips/process.cc
rename : arch/mips/process.hh => src/arch/mips/process.hh
rename : arch/mips/regfile/float_regfile.hh => src/arch/mips/regfile/float_regfile.hh
rename : arch/mips/regfile/int_regfile.hh => src/arch/mips/regfile/int_regfile.hh
rename : arch/mips/regfile/misc_regfile.hh => src/arch/mips/regfile/misc_regfile.hh
rename : arch/mips/regfile/regfile.hh => src/arch/mips/regfile/regfile.hh
rename : arch/mips/stacktrace.hh => src/arch/mips/stacktrace.hh
rename : arch/mips/types.hh => src/arch/mips/types.hh
rename : arch/mips/utility.hh => src/arch/mips/utility.hh
rename : arch/sparc/SConscript => src/arch/sparc/SConscript
rename : arch/sparc/faults.cc => src/arch/sparc/faults.cc
rename : arch/sparc/faults.hh => src/arch/sparc/faults.hh
rename : arch/sparc/isa/base.isa => src/arch/sparc/isa/base.isa
rename : arch/sparc/isa/bitfields.isa => src/arch/sparc/isa/bitfields.isa
rename : arch/sparc/isa/decoder.isa => src/arch/sparc/isa/decoder.isa
rename : arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats.isa
rename : arch/sparc/isa/formats/basic.isa => src/arch/sparc/isa/formats/basic.isa
rename : arch/sparc/isa/formats/branch.isa => src/arch/sparc/isa/formats/branch.isa
rename : arch/sparc/isa/formats/integerop.isa => src/arch/sparc/isa/formats/integerop.isa
rename : arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem.isa
rename : arch/sparc/isa/formats/nop.isa => src/arch/sparc/isa/formats/nop.isa
rename : arch/sparc/isa/formats/priv.isa => src/arch/sparc/isa/formats/priv.isa
rename : arch/sparc/isa/formats/trap.isa => src/arch/sparc/isa/formats/trap.isa
rename : arch/sparc/isa/formats/unknown.isa => src/arch/sparc/isa/formats/unknown.isa
rename : arch/sparc/isa/includes.isa => src/arch/sparc/isa/includes.isa
rename : arch/sparc/isa/main.isa => src/arch/sparc/isa/main.isa
rename : arch/sparc/isa/operands.isa => src/arch/sparc/isa/operands.isa
rename : arch/sparc/isa_traits.hh => src/arch/sparc/isa_traits.hh
rename : arch/sparc/linux/linux.cc => src/arch/sparc/linux/linux.cc
rename : arch/sparc/linux/linux.hh => src/arch/sparc/linux/linux.hh
rename : arch/sparc/linux/process.cc => src/arch/sparc/linux/process.cc
rename : arch/sparc/linux/process.hh => src/arch/sparc/linux/process.hh
rename : arch/sparc/process.cc => src/arch/sparc/process.cc
rename : arch/sparc/process.hh => src/arch/sparc/process.hh
rename : arch/sparc/regfile.hh => src/arch/sparc/regfile.hh
rename : arch/sparc/solaris/process.cc => src/arch/sparc/solaris/process.cc
rename : arch/sparc/solaris/process.hh => src/arch/sparc/solaris/process.hh
rename : arch/sparc/solaris/solaris.cc => src/arch/sparc/solaris/solaris.cc
rename : arch/sparc/solaris/solaris.hh => src/arch/sparc/solaris/solaris.hh
rename : arch/sparc/stacktrace.hh => src/arch/sparc/stacktrace.hh
rename : arch/sparc/system.cc => src/arch/sparc/system.cc
rename : arch/sparc/system.hh => src/arch/sparc/system.hh
rename : arch/sparc/utility.hh => src/arch/sparc/utility.hh
rename : base/bitfield.hh => src/base/bitfield.hh
rename : base/callback.hh => src/base/callback.hh
rename : base/chunk_generator.hh => src/base/chunk_generator.hh
rename : base/circlebuf.cc => src/base/circlebuf.cc
rename : base/circlebuf.hh => src/base/circlebuf.hh
rename : base/compression/lzss_compression.cc => src/base/compression/lzss_compression.cc
rename : base/compression/lzss_compression.hh => src/base/compression/lzss_compression.hh
rename : base/compression/null_compression.hh => src/base/compression/null_compression.hh
rename : base/cprintf.cc => src/base/cprintf.cc
rename : base/cprintf.hh => src/base/cprintf.hh
rename : base/cprintf_formats.hh => src/base/cprintf_formats.hh
rename : base/crc.cc => src/base/crc.cc
rename : base/crc.hh => src/base/crc.hh
rename : base/date.cc => src/base/date.cc
rename : base/dbl_list.hh => src/base/dbl_list.hh
rename : base/endian.hh => src/base/endian.hh
rename : base/fast_alloc.cc => src/base/fast_alloc.cc
rename : base/fast_alloc.hh => src/base/fast_alloc.hh
rename : base/fenv.hh => src/base/fenv.hh
rename : base/fifo_buffer.cc => src/base/fifo_buffer.cc
rename : base/fifo_buffer.hh => src/base/fifo_buffer.hh
rename : base/hashmap.hh => src/base/hashmap.hh
rename : base/hostinfo.cc => src/base/hostinfo.cc
rename : base/hostinfo.hh => src/base/hostinfo.hh
rename : base/hybrid_pred.cc => src/base/hybrid_pred.cc
rename : base/hybrid_pred.hh => src/base/hybrid_pred.hh
rename : base/inet.cc => src/base/inet.cc
rename : base/inet.hh => src/base/inet.hh
rename : base/inifile.cc => src/base/inifile.cc
rename : base/inifile.hh => src/base/inifile.hh
rename : base/intmath.cc => src/base/intmath.cc
rename : base/intmath.hh => src/base/intmath.hh
rename : base/kgdb.h => src/base/kgdb.h
rename : base/loader/aout_object.cc => src/base/loader/aout_object.cc
rename : base/loader/aout_object.hh => src/base/loader/aout_object.hh
rename : base/loader/coff_sym.h => src/base/loader/coff_sym.h
rename : base/loader/coff_symconst.h => src/base/loader/coff_symconst.h
rename : base/loader/ecoff_object.cc => src/base/loader/ecoff_object.cc
rename : base/loader/ecoff_object.hh => src/base/loader/ecoff_object.hh
rename : base/loader/elf_object.cc => src/base/loader/elf_object.cc
rename : base/loader/elf_object.hh => src/base/loader/elf_object.hh
rename : base/loader/exec_aout.h => src/base/loader/exec_aout.h
rename : base/loader/exec_ecoff.h => src/base/loader/exec_ecoff.h
rename : base/loader/object_file.cc => src/base/loader/object_file.cc
rename : base/loader/object_file.hh => src/base/loader/object_file.hh
rename : base/loader/symtab.cc => src/base/loader/symtab.cc
rename : base/loader/symtab.hh => src/base/loader/symtab.hh
rename : base/match.cc => src/base/match.cc
rename : base/match.hh => src/base/match.hh
rename : base/misc.cc => src/base/misc.cc
rename : base/misc.hh => src/base/misc.hh
rename : base/mod_num.hh => src/base/mod_num.hh
rename : base/mysql.cc => src/base/mysql.cc
rename : base/mysql.hh => src/base/mysql.hh
rename : base/output.cc => src/base/output.cc
rename : base/output.hh => src/base/output.hh
rename : base/pollevent.cc => src/base/pollevent.cc
rename : base/pollevent.hh => src/base/pollevent.hh
rename : base/predictor.hh => src/base/predictor.hh
rename : base/random.cc => src/base/random.cc
rename : base/random.hh => src/base/random.hh
rename : base/range.cc => src/base/range.cc
rename : base/range.hh => src/base/range.hh
rename : base/refcnt.hh => src/base/refcnt.hh
rename : base/remote_gdb.cc => src/base/remote_gdb.cc
rename : base/remote_gdb.hh => src/base/remote_gdb.hh
rename : base/res_list.hh => src/base/res_list.hh
rename : base/sat_counter.cc => src/base/sat_counter.cc
rename : base/sat_counter.hh => src/base/sat_counter.hh
rename : base/sched_list.hh => src/base/sched_list.hh
rename : base/socket.cc => src/base/socket.cc
rename : base/socket.hh => src/base/socket.hh
rename : base/statistics.cc => src/base/statistics.cc
rename : base/statistics.hh => src/base/statistics.hh
rename : base/stats/events.cc => src/base/stats/events.cc
rename : base/stats/events.hh => src/base/stats/events.hh
rename : base/stats/flags.hh => src/base/stats/flags.hh
rename : base/stats/mysql.cc => src/base/stats/mysql.cc
rename : base/stats/mysql.hh => src/base/stats/mysql.hh
rename : base/stats/mysql_run.hh => src/base/stats/mysql_run.hh
rename : base/stats/output.hh => src/base/stats/output.hh
rename : base/stats/statdb.cc => src/base/stats/statdb.cc
rename : base/stats/statdb.hh => src/base/stats/statdb.hh
rename : base/stats/text.cc => src/base/stats/text.cc
rename : base/stats/text.hh => src/base/stats/text.hh
rename : base/stats/types.hh => src/base/stats/types.hh
rename : base/stats/visit.cc => src/base/stats/visit.cc
rename : base/stats/visit.hh => src/base/stats/visit.hh
rename : base/str.cc => src/base/str.cc
rename : base/str.hh => src/base/str.hh
rename : base/time.cc => src/base/time.cc
rename : base/time.hh => src/base/time.hh
rename : base/timebuf.hh => src/base/timebuf.hh
rename : base/trace.cc => src/base/trace.cc
rename : base/trace.hh => src/base/trace.hh
rename : base/traceflags.py => src/base/traceflags.py
rename : base/userinfo.cc => src/base/userinfo.cc
rename : base/userinfo.hh => src/base/userinfo.hh
rename : cpu/SConscript => src/cpu/SConscript
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc
rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh
rename : cpu/cpu_models.py => src/cpu/cpu_models.py
rename : cpu/exec_context.hh => src/cpu/exec_context.hh
rename : cpu/exetrace.cc => src/cpu/exetrace.cc
rename : cpu/exetrace.hh => src/cpu/exetrace.hh
rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh
rename : cpu/intr_control.cc => src/cpu/intr_control.cc
rename : cpu/intr_control.hh => src/cpu/intr_control.hh
rename : cpu/memtest/memtest.cc => src/cpu/memtest/memtest.cc
rename : cpu/memtest/memtest.hh => src/cpu/memtest/memtest.hh
rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc
rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh
rename : cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha_cpu.cc
rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc
rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh
rename : cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha_dyn_inst.cc
rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh
rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh
rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh
rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc
rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh
rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh
rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc
rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh
rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh
rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc
rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh
rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh
rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc
rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh
rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh
rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc
rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc
rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh
rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc
rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc
rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh
rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh
rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc
rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh
rename : cpu/o3/rob.cc => src/cpu/o3/rob.cc
rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh
rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh
rename : cpu/o3/sat_counter.cc => src/cpu/o3/sat_counter.cc
rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh
rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc
rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/op_class.cc => src/cpu/op_class.cc
rename : cpu/op_class.hh => src/cpu/op_class.hh
rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/ea_list.cc => src/cpu/ozone/ea_list.cc
rename : cpu/ozone/ea_list.hh => src/cpu/ozone/ea_list.hh
rename : cpu/pc_event.cc => src/cpu/pc_event.cc
rename : cpu/pc_event.hh => src/cpu/pc_event.hh
rename : cpu/profile.cc => src/cpu/profile.cc
rename : cpu/profile.hh => src/cpu/profile.hh
rename : cpu/simple/atomic.cc => src/cpu/simple/atomic.cc
rename : cpu/simple/atomic.hh => src/cpu/simple/atomic.hh
rename : cpu/simple/base.cc => src/cpu/simple/base.cc
rename : cpu/simple/base.hh => src/cpu/simple/base.hh
rename : cpu/simple/timing.cc => src/cpu/simple/timing.cc
rename : cpu/simple/timing.hh => src/cpu/simple/timing.hh
rename : cpu/smt.hh => src/cpu/smt.hh
rename : cpu/static_inst.cc => src/cpu/static_inst.cc
rename : cpu/static_inst.hh => src/cpu/static_inst.hh
rename : cpu/trace/opt_cpu.cc => src/cpu/trace/opt_cpu.cc
rename : cpu/trace/opt_cpu.hh => src/cpu/trace/opt_cpu.hh
rename : cpu/trace/reader/ibm_reader.cc => src/cpu/trace/reader/ibm_reader.cc
rename : cpu/trace/reader/ibm_reader.hh => src/cpu/trace/reader/ibm_reader.hh
rename : cpu/trace/reader/itx_reader.cc => src/cpu/trace/reader/itx_reader.cc
rename : cpu/trace/reader/itx_reader.hh => src/cpu/trace/reader/itx_reader.hh
rename : cpu/trace/reader/m5_reader.cc => src/cpu/trace/reader/m5_reader.cc
rename : cpu/trace/reader/m5_reader.hh => src/cpu/trace/reader/m5_reader.hh
rename : cpu/trace/reader/mem_trace_reader.cc => src/cpu/trace/reader/mem_trace_reader.cc
rename : cpu/trace/reader/mem_trace_reader.hh => src/cpu/trace/reader/mem_trace_reader.hh
rename : cpu/trace/trace_cpu.cc => src/cpu/trace/trace_cpu.cc
rename : cpu/trace/trace_cpu.hh => src/cpu/trace/trace_cpu.hh
rename : dev/alpha_access.h => src/dev/alpha_access.h
rename : dev/alpha_console.cc => src/dev/alpha_console.cc
rename : dev/alpha_console.hh => src/dev/alpha_console.hh
rename : dev/baddev.cc => src/dev/baddev.cc
rename : dev/baddev.hh => src/dev/baddev.hh
rename : dev/disk_image.cc => src/dev/disk_image.cc
rename : dev/disk_image.hh => src/dev/disk_image.hh
rename : dev/etherbus.cc => src/dev/etherbus.cc
rename : dev/etherbus.hh => src/dev/etherbus.hh
rename : dev/etherdump.cc => src/dev/etherdump.cc
rename : dev/etherdump.hh => src/dev/etherdump.hh
rename : dev/etherint.cc => src/dev/etherint.cc
rename : dev/etherint.hh => src/dev/etherint.hh
rename : dev/etherlink.cc => src/dev/etherlink.cc
rename : dev/etherlink.hh => src/dev/etherlink.hh
rename : dev/etherpkt.cc => src/dev/etherpkt.cc
rename : dev/etherpkt.hh => src/dev/etherpkt.hh
rename : dev/ethertap.cc => src/dev/ethertap.cc
rename : dev/ethertap.hh => src/dev/ethertap.hh
rename : dev/ide_atareg.h => src/dev/ide_atareg.h
rename : dev/ide_ctrl.cc => src/dev/ide_ctrl.cc
rename : dev/ide_ctrl.hh => src/dev/ide_ctrl.hh
rename : dev/ide_disk.cc => src/dev/ide_disk.cc
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : dev/ide_wdcreg.h => src/dev/ide_wdcreg.h
rename : dev/io_device.cc => src/dev/io_device.cc
rename : dev/io_device.hh => src/dev/io_device.hh
rename : dev/isa_fake.cc => src/dev/isa_fake.cc
rename : dev/isa_fake.hh => src/dev/isa_fake.hh
rename : dev/ns_gige.cc => src/dev/ns_gige.cc
rename : dev/ns_gige.hh => src/dev/ns_gige.hh
rename : dev/ns_gige_reg.h => src/dev/ns_gige_reg.h
rename : dev/pciconfigall.cc => src/dev/pciconfigall.cc
rename : dev/pciconfigall.hh => src/dev/pciconfigall.hh
rename : dev/pcidev.cc => src/dev/pcidev.cc
rename : dev/pcidev.hh => src/dev/pcidev.hh
rename : dev/pcireg.h => src/dev/pcireg.h
rename : dev/pitreg.h => src/dev/pitreg.h
rename : dev/pktfifo.cc => src/dev/pktfifo.cc
rename : dev/pktfifo.hh => src/dev/pktfifo.hh
rename : dev/platform.cc => src/dev/platform.cc
rename : dev/platform.hh => src/dev/platform.hh
rename : dev/rtcreg.h => src/dev/rtcreg.h
rename : dev/simconsole.cc => src/dev/simconsole.cc
rename : dev/simconsole.hh => src/dev/simconsole.hh
rename : dev/simple_disk.cc => src/dev/simple_disk.cc
rename : dev/simple_disk.hh => src/dev/simple_disk.hh
rename : dev/sinic.cc => src/dev/sinic.cc
rename : dev/sinic.hh => src/dev/sinic.hh
rename : dev/sinicreg.hh => src/dev/sinicreg.hh
rename : dev/tsunami.cc => src/dev/tsunami.cc
rename : dev/tsunami.hh => src/dev/tsunami.hh
rename : dev/tsunami_cchip.cc => src/dev/tsunami_cchip.cc
rename : dev/tsunami_cchip.hh => src/dev/tsunami_cchip.hh
rename : dev/tsunami_io.cc => src/dev/tsunami_io.cc
rename : dev/tsunami_io.hh => src/dev/tsunami_io.hh
rename : dev/tsunami_pchip.cc => src/dev/tsunami_pchip.cc
rename : dev/tsunami_pchip.hh => src/dev/tsunami_pchip.hh
rename : dev/tsunamireg.h => src/dev/tsunamireg.h
rename : dev/uart.cc => src/dev/uart.cc
rename : dev/uart.hh => src/dev/uart.hh
rename : dev/uart8250.cc => src/dev/uart8250.cc
rename : dev/uart8250.hh => src/dev/uart8250.hh
rename : kern/kernel_stats.cc => src/kern/kernel_stats.cc
rename : kern/kernel_stats.hh => src/kern/kernel_stats.hh
rename : kern/linux/events.cc => src/kern/linux/events.cc
rename : kern/linux/events.hh => src/kern/linux/events.hh
rename : kern/linux/linux.hh => src/kern/linux/linux.hh
rename : kern/linux/linux_syscalls.cc => src/kern/linux/linux_syscalls.cc
rename : kern/linux/linux_syscalls.hh => src/kern/linux/linux_syscalls.hh
rename : kern/linux/printk.cc => src/kern/linux/printk.cc
rename : kern/linux/printk.hh => src/kern/linux/printk.hh
rename : kern/linux/sched.hh => src/kern/linux/sched.hh
rename : kern/solaris/solaris.hh => src/kern/solaris/solaris.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/system_events.hh => src/kern/system_events.hh
rename : kern/tru64/dump_mbuf.cc => src/kern/tru64/dump_mbuf.cc
rename : kern/tru64/dump_mbuf.hh => src/kern/tru64/dump_mbuf.hh
rename : kern/tru64/mbuf.hh => src/kern/tru64/mbuf.hh
rename : kern/tru64/printf.cc => src/kern/tru64/printf.cc
rename : kern/tru64/printf.hh => src/kern/tru64/printf.hh
rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh
rename : kern/tru64/tru64_events.cc => src/kern/tru64/tru64_events.cc
rename : kern/tru64/tru64_events.hh => src/kern/tru64/tru64_events.hh
rename : kern/tru64/tru64_syscalls.cc => src/kern/tru64/tru64_syscalls.cc
rename : kern/tru64/tru64_syscalls.hh => src/kern/tru64/tru64_syscalls.hh
rename : mem/bridge.cc => src/mem/bridge.cc
rename : mem/bridge.hh => src/mem/bridge.hh
rename : mem/bus.cc => src/mem/bus.cc
rename : mem/bus.hh => src/mem/bus.hh
rename : mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher_impl.hh
rename : mem/config/prefetch.hh => src/mem/config/prefetch.hh
rename : mem/mem_object.cc => src/mem/mem_object.cc
rename : mem/mem_object.hh => src/mem/mem_object.hh
rename : mem/packet.cc => src/mem/packet.cc
rename : mem/packet.hh => src/mem/packet.hh
rename : mem/page_table.cc => src/mem/page_table.cc
rename : mem/page_table.hh => src/mem/page_table.hh
rename : mem/physical.cc => src/mem/physical.cc
rename : mem/physical.hh => src/mem/physical.hh
rename : mem/port.cc => src/mem/port.cc
rename : mem/port.hh => src/mem/port.hh
rename : mem/request.hh => src/mem/request.hh
rename : mem/translating_port.cc => src/mem/translating_port.cc
rename : mem/translating_port.hh => src/mem/translating_port.hh
rename : mem/vport.cc => src/mem/vport.cc
rename : mem/vport.hh => src/mem/vport.hh
rename : python/SConscript => src/python/SConscript
rename : python/m5/__init__.py => src/python/m5/__init__.py
rename : python/m5/config.py => src/python/m5/config.py
rename : python/m5/convert.py => src/python/m5/convert.py
rename : python/m5/multidict.py => src/python/m5/multidict.py
rename : python/m5/objects/AlphaConsole.py => src/python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.py => src/python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.py => src/python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.py => src/python/m5/objects/BaseCache.py
rename : python/m5/objects/Bridge.py => src/python/m5/objects/Bridge.py
rename : python/m5/objects/Bus.py => src/python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.py => src/python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.py => src/python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.py => src/python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.py => src/python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.py => src/python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.py => src/python/m5/objects/IntrControl.py
rename : python/m5/objects/MemObject.py => src/python/m5/objects/MemObject.py
rename : python/m5/objects/MemTest.py => src/python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.py => src/python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.py => src/python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.py => src/python/m5/objects/Platform.py
rename : python/m5/objects/Process.py => src/python/m5/objects/Process.py
rename : python/m5/objects/Repl.py => src/python/m5/objects/Repl.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.py => src/python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.py => src/python/m5/objects/SimpleDisk.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : python/m5/objects/Tsunami.py => src/python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.py => src/python/m5/objects/Uart.py
rename : python/m5/smartdict.py => src/python/m5/smartdict.py
rename : sim/async.hh => src/sim/async.hh
rename : sim/builder.cc => src/sim/builder.cc
rename : sim/builder.hh => src/sim/builder.hh
rename : sim/byteswap.hh => src/sim/byteswap.hh
rename : sim/debug.cc => src/sim/debug.cc
rename : sim/debug.hh => src/sim/debug.hh
rename : sim/eventq.cc => src/sim/eventq.cc
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/faults.cc => src/sim/faults.cc
rename : sim/faults.hh => src/sim/faults.hh
rename : sim/host.hh => src/sim/host.hh
rename : sim/main.cc => src/sim/main.cc
rename : sim/param.cc => src/sim/param.cc
rename : sim/param.hh => src/sim/param.hh
rename : sim/process.cc => src/sim/process.cc
rename : sim/process.hh => src/sim/process.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/root.cc => src/sim/root.cc
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/serialize.hh => src/sim/serialize.hh
rename : sim/sim_events.cc => src/sim/sim_events.cc
rename : sim/sim_events.hh => src/sim/sim_events.hh
rename : sim/sim_exit.hh => src/sim/sim_exit.hh
rename : sim/sim_object.cc => src/sim/sim_object.cc
rename : sim/sim_object.hh => src/sim/sim_object.hh
rename : sim/startup.cc => src/sim/startup.cc
rename : sim/startup.hh => src/sim/startup.hh
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/stats.hh => src/sim/stats.hh
rename : sim/syscall_emul.cc => src/sim/syscall_emul.cc
rename : sim/syscall_emul.hh => src/sim/syscall_emul.hh
rename : sim/system.cc => src/sim/system.cc
rename : sim/system.hh => src/sim/system.hh
rename : sim/vptr.hh => src/sim/vptr.hh
rename : test/Makefile => src/unittest/Makefile
rename : test/bitvectest.cc => src/unittest/bitvectest.cc
rename : test/circletest.cc => src/unittest/circletest.cc
rename : test/cprintftest.cc => src/unittest/cprintftest.cc
rename : test/foo.ini => src/unittest/foo.ini
rename : test/genini.py => src/unittest/genini.py
rename : test/initest.cc => src/unittest/initest.cc
rename : test/initest.ini => src/unittest/initest.ini
rename : test/lru_test.cc => src/unittest/lru_test.cc
rename : test/nmtest.cc => src/unittest/nmtest.cc
rename : test/offtest.cc => src/unittest/offtest.cc
rename : test/paramtest.cc => src/unittest/paramtest.cc
rename : test/rangetest.cc => src/unittest/rangetest.cc
rename : test/sized_test.cc => src/unittest/sized_test.cc
rename : test/stattest.cc => src/unittest/stattest.cc
rename : test/strnumtest.cc => src/unittest/strnumtest.cc
rename : test/symtest.cc => src/unittest/symtest.cc
rename : test/tokentest.cc => src/unittest/tokentest.cc
rename : test/tracetest.cc => src/unittest/tracetest.cc
extra : convert_revision : cab6a5271ca1b368193cd948e5d3dcc47ab1bd48

1 files changed, 812 insertions, 0 deletions

diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
new file mode 100644
index 000000000..5169a332f
--- /dev/null
+++ b/src/arch/sparc/regfile.hh
@@ -0,0 +1,812 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_SPARC_REGFILE_HH__
+#define __ARCH_SPARC_REGFILE_HH__
+
+#include "arch/sparc/faults.hh"
+#include "base/trace.hh"
+#include "sim/byteswap.hh"
+#include "sim/host.hh"
+
+class Checkpoint;
+
+namespace SparcISA
+{
+
+    typedef uint8_t  RegIndex;
+
+    // MAXTL - maximum trap level
+    const int MaxTL = 4;
+
+    // NWINDOWS - number of register windows, can be 3 to 32
+    const int NWindows = 32;
+
+    class IntRegFile
+    {
+      protected:
+        static const int FrameOffsetBits = 3;
+        static const int FrameNumBits = 2;
+
+        static const int RegsPerFrame = 1 << FrameOffsetBits;
+        static const int FrameNumMask =
+                (FrameNumBits == sizeof(int)) ?
+                (unsigned int)(-1) :
+                (1 << FrameNumBits) - 1;
+        static const int FrameOffsetMask =
+                (FrameOffsetBits == sizeof(int)) ?
+                (unsigned int)(-1) :
+                (1 << FrameOffsetBits) - 1;
+
+        IntReg regGlobals[RegsPerFrame];
+        IntReg altGlobals[RegsPerFrame];
+        IntReg regSegments[2 * NWindows][RegsPerFrame];
+
+        enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames};
+
+        IntReg * regView[NumFrames];
+
+        static const int RegGlobalOffset = 0;
+        static const int AltGlobalOffset = 8;
+        static const int FrameOffset = 16;
+        int offset[NumFrames];
+
+      public:
+
+        int flattenIndex(int reg)
+        {
+            int flatIndex = offset[reg >> FrameOffsetBits]
+                | (reg & FrameOffsetMask);
+            DPRINTF(Sparc, "Flattened index %d into %d.\n", reg, flatIndex);
+            return flatIndex;
+        }
+
+        void clear()
+        {
+            bzero(regGlobals, sizeof(regGlobals));
+            bzero(altGlobals, sizeof(altGlobals));
+            for(int x = 0; x < 2 * NWindows; x++)
+                bzero(regSegments[x], sizeof(regSegments[x]));
+        }
+
+        IntRegFile()
+        {
+            offset[Globals] = 0;
+            regView[Globals] = regGlobals;
+            setCWP(0);
+            clear();
+        }
+
+        IntReg readReg(int intReg)
+        {
+            IntReg val =
+                regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask];
+            DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val);
+            return val;
+        }
+
+        Fault setReg(int intReg, const IntReg &val)
+        {
+            if(intReg)
+                DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val);
+            regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val;
+            return NoFault;
+        }
+
+        //This doesn't effect the actual CWP register.
+        //It's purpose is to adjust the view of the register file
+        //to what it would be if CWP = cwp.
+        void setCWP(int cwp)
+        {
+            int index = ((NWindows - cwp) % NWindows) * 2;
+            offset[Outputs] = FrameOffset + (index * RegsPerFrame);
+            offset[Locals] = FrameOffset + ((index+1) * RegsPerFrame);
+            offset[Inputs] = FrameOffset +
+                (((index+2) % (NWindows * 2)) * RegsPerFrame);
+            regView[Outputs] = regSegments[index];
+            regView[Locals] = regSegments[index+1];
+            regView[Inputs] = regSegments[(index+2) % (NWindows * 2)];
+
+            DPRINTF(Sparc, "Changed the CWP value to %d\n", cwp);
+        }
+
+        void setAltGlobals(bool useAlt)
+        {
+            DPRINTF(Sparc, "Now using %s globals",
+                    useAlt ? "alternate" : "regular");
+            regView[Globals] = useAlt ? altGlobals : regGlobals;
+
+            // You have not included an out-of-class definition of your static
+            // members. See [9.4.2]/4 and about a billion gcc bug reports. If
+            // statements get around the problem through some magic, and than
+            // seems nicer that putting a definition of them in a c file
+            // somewhere.
+            if (useAlt)
+                offset[Globals] = AltGlobalOffset;
+            else
+                offset[Globals] = RegGlobalOffset;
+        }
+
+        void serialize(std::ostream &os);
+
+        void unserialize(Checkpoint *cp, const std::string &section);
+    };
+
+    typedef float float32_t;
+    typedef double float64_t;
+    //FIXME long double refers to a 10 byte float, rather than a
+    //16 byte float as required. This data type may have to be emulated.
+    typedef double float128_t;
+
+    class FloatRegFile
+    {
+      public:
+        static const int SingleWidth = 32;
+        static const int DoubleWidth = 64;
+        static const int QuadWidth = 128;
+
+      protected:
+
+        //Since the floating point registers overlap each other,
+        //A generic storage space is used. The float to be returned is
+        //pulled from the appropriate section of this region.
+        char regSpace[SingleWidth / 8 * NumFloatRegs];
+
+      public:
+
+        void clear()
+        {
+            bzero(regSpace, sizeof(regSpace));
+        }
+
+        FloatReg readReg(int floatReg, int width)
+        {
+            //In each of these cases, we have to copy the value into a temporary
+            //variable. This is because we may otherwise try to access an
+            //unaligned portion of memory.
+            switch(width)
+            {
+              case SingleWidth:
+                float32_t result32;
+                memcpy(&result32, regSpace + 4 * floatReg, width);
+                return htog(result32);
+              case DoubleWidth:
+                float64_t result64;
+                memcpy(&result64, regSpace + 4 * floatReg, width);
+                return htog(result64);
+              case QuadWidth:
+                float128_t result128;
+                memcpy(&result128, regSpace + 4 * floatReg, width);
+                return htog(result128);
+              default:
+                panic("Attempted to read a %d bit floating point register!", width);
+            }
+        }
+
+        FloatRegBits readRegBits(int floatReg, int width)
+        {
+            //In each of these cases, we have to copy the value into a temporary
+            //variable. This is because we may otherwise try to access an
+            //unaligned portion of memory.
+            switch(width)
+            {
+              case SingleWidth:
+                uint32_t result32;
+                memcpy(&result32, regSpace + 4 * floatReg, width);
+                return htog(result32);
+              case DoubleWidth:
+                uint64_t result64;
+                memcpy(&result64, regSpace + 4 * floatReg, width);
+                return htog(result64);
+              case QuadWidth:
+                uint64_t result128;
+                memcpy(&result128, regSpace + 4 * floatReg, width);
+                return htog(result128);
+              default:
+                panic("Attempted to read a %d bit floating point register!", width);
+            }
+        }
+
+        Fault setReg(int floatReg, const FloatReg &val, int width)
+        {
+            //In each of these cases, we have to copy the value into a temporary
+            //variable. This is because we may otherwise try to access an
+            //unaligned portion of memory.
+            switch(width)
+            {
+              case SingleWidth:
+                uint32_t result32 = gtoh((uint32_t)val);
+                memcpy(regSpace + 4 * floatReg, &result32, width);
+              case DoubleWidth:
+                uint64_t result64 = gtoh((uint64_t)val);
+                memcpy(regSpace + 4 * floatReg, &result64, width);
+              case QuadWidth:
+                uint64_t result128 = gtoh((uint64_t)val);
+                memcpy(regSpace + 4 * floatReg, &result128, width);
+              default:
+                panic("Attempted to read a %d bit floating point register!", width);
+            }
+            return NoFault;
+        }
+
+        Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
+        {
+            //In each of these cases, we have to copy the value into a temporary
+            //variable. This is because we may otherwise try to access an
+            //unaligned portion of memory.
+            switch(width)
+            {
+              case SingleWidth:
+                uint32_t result32 = gtoh((uint32_t)val);
+                memcpy(regSpace + 4 * floatReg, &result32, width);
+              case DoubleWidth:
+                uint64_t result64 = gtoh((uint64_t)val);
+                memcpy(regSpace + 4 * floatReg, &result64, width);
+              case QuadWidth:
+                uint64_t result128 = gtoh((uint64_t)val);
+                memcpy(regSpace + 4 * floatReg, &result128, width);
+              default:
+                panic("Attempted to read a %d bit floating point register!", width);
+            }
+            return NoFault;
+        }
+
+        void serialize(std::ostream &os);
+
+        void unserialize(Checkpoint *cp, const std::string &section);
+    };
+
+    enum MiscRegIndex
+    {
+        MISCREG_PSTATE,
+        MISCREG_PSTATE_AG,
+        MISCREG_PSTATE_IE,
+        MISCREG_PSTATE_PRIV,
+        MISCREG_PSTATE_AM,
+        MISCREG_PSTATE_PEF,
+        MISCREG_PSTATE_RED,
+        MISCREG_PSTATE_MM,
+        MISCREG_PSTATE_TLE,
+        MISCREG_PSTATE_CLE,
+        MISCREG_TBA,
+        MISCREG_Y,
+        MISCREG_Y_VALUE,
+        MISCREG_PIL,
+        MISCREG_CWP,
+        MISCREG_TT_BASE,
+        MISCREG_TT_END = MISCREG_TT_BASE + MaxTL,
+        MISCREG_CCR,
+        MISCREG_CCR_ICC,
+        MISCREG_CCR_ICC_C,
+        MISCREG_CCR_ICC_V,
+        MISCREG_CCR_ICC_Z,
+        MISCREG_CCR_ICC_N,
+        MISCREG_CCR_XCC,
+        MISCREG_CCR_XCC_C,
+        MISCREG_CCR_XCC_V,
+        MISCREG_CCR_XCC_Z,
+        MISCREG_CCR_XCC_N,
+        MISCREG_ASI,
+        MISCREG_TL,
+        MISCREG_TPC_BASE,
+        MISCREG_TPC_END = MISCREG_TPC_BASE + MaxTL,
+        MISCREG_TNPC_BASE,
+        MISCREG_TNPC_END = MISCREG_TNPC_BASE + MaxTL,
+        MISCREG_TSTATE_BASE,
+        MISCREG_TSTATE_END = MISCREG_TSTATE_BASE + MaxTL,
+        MISCREG_TSTATE_CWP_BASE,
+        MISCREG_TSTATE_CWP_END = MISCREG_TSTATE_CWP_BASE + MaxTL,
+        MISCREG_TSTATE_PSTATE_BASE,
+        MISCREG_TSTATE_PSTATE_END = MISCREG_TSTATE_PSTATE_BASE + MaxTL,
+        MISCREG_TSTATE_ASI_BASE,
+        MISCREG_TSTATE_ASI_END = MISCREG_TSTATE_ASI_BASE + MaxTL,
+        MISCREG_TSTATE_CCR_BASE,
+        MISCREG_TSTATE_CCR_END = MISCREG_TSTATE_CCR_BASE + MaxTL,
+        MISCREG_TICK,
+        MISCREG_TICK_COUNTER,
+        MISCREG_TICK_NPT,
+        MISCREG_CANSAVE,
+        MISCREG_CANRESTORE,
+        MISCREG_OTHERWIN,
+        MISCREG_CLEANWIN,
+        MISCREG_WSTATE,
+        MISCREG_WSTATE_NORMAL,
+        MISCREG_WSTATE_OTHER,
+        MISCREG_VER,
+        MISCREG_VER_MAXWIN,
+        MISCREG_VER_MAXTL,
+        MISCREG_VER_MASK,
+        MISCREG_VER_IMPL,
+        MISCREG_VER_MANUF,
+        MISCREG_FSR,
+        MISCREG_FSR_CEXC,
+        MISCREG_FSR_CEXC_NXC,
+        MISCREG_FSR_CEXC_DZC,
+        MISCREG_FSR_CEXC_UFC,
+        MISCREG_FSR_CEXC_OFC,
+        MISCREG_FSR_CEXC_NVC,
+        MISCREG_FSR_AEXC,
+        MISCREG_FSR_AEXC_NXC,
+        MISCREG_FSR_AEXC_DZC,
+        MISCREG_FSR_AEXC_UFC,
+        MISCREG_FSR_AEXC_OFC,
+        MISCREG_FSR_AEXC_NVC,
+        MISCREG_FSR_FCC0,
+        MISCREG_FSR_QNE,
+        MISCREG_FSR_FTT,
+        MISCREG_FSR_VER,
+        MISCREG_FSR_NS,
+        MISCREG_FSR_TEM,
+        MISCREG_FSR_TEM_NXM,
+        MISCREG_FSR_TEM_DZM,
+        MISCREG_FSR_TEM_UFM,
+        MISCREG_FSR_TEM_OFM,
+        MISCREG_FSR_TEM_NVM,
+        MISCREG_FSR_RD,
+        MISCREG_FSR_FCC1,
+        MISCREG_FSR_FCC2,
+        MISCREG_FSR_FCC3,
+        MISCREG_FPRS,
+        MISCREG_FPRS_DL,
+        MISCREG_FPRS_DU,
+        MISCREG_FPRS_FEF,
+        numMiscRegs
+    };
+
+    // The control registers, broken out into fields
+    class MiscRegFile
+    {
+      private:
+        union
+        {
+            uint16_t pstate;		// Process State Register
+            struct
+            {
+                uint16_t ag:1;		// Alternate Globals
+                uint16_t ie:1;		// Interrupt enable
+                uint16_t priv:1;	// Privelege mode
+                uint16_t am:1;		// Address mask
+                uint16_t pef:1;		// PSTATE enable floating-point
+                uint16_t red:1;		// RED (reset, error, debug) state
+                uint16_t mm:2;		// Memory Model
+                uint16_t tle:1;		// Trap little-endian
+                uint16_t cle:1;		// Current little-endian
+            } pstateFields;
+        };
+        uint64_t tba;		// Trap Base Address
+        union
+        {
+            uint64_t y;		// Y (used in obsolete multiplication)
+            struct
+            {
+                uint64_t value:32;	// The actual value stored in y
+                uint64_t :32;	// reserved bits
+            } yFields;
+        };
+        uint8_t pil;		// Process Interrupt Register
+        uint8_t cwp;		// Current Window Pointer
+        uint16_t tt[MaxTL];	// Trap Type (Type of trap which occured
+                                // on the previous level)
+        union
+        {
+            uint8_t	ccr;		// Condition Code Register
+            struct
+            {
+                union
+                {
+                    uint8_t icc:4;	// 32-bit condition codes
+                    struct
+                    {
+                        uint8_t c:1;	// Carry
+                        uint8_t v:1;	// Overflow
+                        uint8_t z:1;	// Zero
+                        uint8_t n:1;	// Negative
+                    } iccFields;
+                };
+                union
+                {
+                    uint8_t xcc:4;	// 64-bit condition codes
+                    struct
+                    {
+                        uint8_t c:1;	// Carry
+                        uint8_t v:1;	// Overflow
+                        uint8_t z:1;	// Zero
+                        uint8_t n:1;	// Negative
+                    } xccFields;
+                };
+            } ccrFields;
+        };
+        uint8_t asi;		// Address Space Identifier
+        uint8_t tl;		// Trap Level
+        uint64_t tpc[MaxTL];	// Trap Program Counter (value from
+                                // previous trap level)
+        uint64_t tnpc[MaxTL];	// Trap Next Program Counter (value from
+                                // previous trap level)
+        union
+        {
+            uint64_t tstate[MaxTL];	// Trap State
+            struct
+            {
+                //Values are from previous trap level
+                uint64_t cwp:5;		// Current Window Pointer
+                uint64_t :2;	// Reserved bits
+                uint64_t pstate:10;	// Process State
+                uint64_t :6;	// Reserved bits
+                uint64_t asi:8;		// Address Space Identifier
+                uint64_t ccr:8;		// Condition Code Register
+            } tstateFields[MaxTL];
+        };
+        union
+        {
+            uint64_t tick;		// Hardware clock-tick counter
+            struct
+            {
+                uint64_t counter:63;	// Clock-tick count
+                uint64_t npt:1;		// Non-priveleged trap
+            } tickFields;
+        };
+        uint8_t cansave;	// Savable windows
+        uint8_t canrestore;	// Restorable windows
+        uint8_t otherwin;	// Other windows
+        uint8_t cleanwin;	// Clean windows
+        union
+        {
+            uint8_t wstate;		// Window State
+            struct
+            {
+                uint8_t normal:3;	// Bits TT<4:2> are set to on a normal
+                                        // register window trap
+                uint8_t other:3;	// Bits TT<4:2> are set to on an "otherwin"
+                                        // register window trap
+            } wstateFields;
+        };
+        union
+        {
+            uint64_t ver;		// Version
+            struct
+            {
+                uint64_t maxwin:5;	// Max CWP value
+                uint64_t :2;	// Reserved bits
+                uint64_t maxtl:8;	// Maximum trap level
+                uint64_t :8;	// Reserved bits
+                uint64_t mask:8;	// Processor mask set revision number
+                uint64_t impl:16;	// Implementation identification number
+                uint64_t manuf:16;	// Manufacturer code
+            } verFields;
+        };
+        union
+        {
+            uint64_t	fsr;	// Floating-Point State Register
+            struct
+            {
+                union
+                {
+                    uint64_t cexc:5;	// Current excpetion
+                    struct
+                    {
+                        uint64_t nxc:1;		// Inexact
+                        uint64_t dzc:1;		// Divide by zero
+                        uint64_t ufc:1;		// Underflow
+                        uint64_t ofc:1;		// Overflow
+                        uint64_t nvc:1;		// Invalid operand
+                    } cexcFields;
+                };
+                union
+                {
+                    uint64_t aexc:5;		// Accrued exception
+                    struct
+                    {
+                        uint64_t nxc:1;		// Inexact
+                        uint64_t dzc:1;		// Divide by zero
+                        uint64_t ufc:1;		// Underflow
+                        uint64_t ofc:1;		// Overflow
+                        uint64_t nvc:1;		// Invalid operand
+                    } aexcFields;
+                };
+                uint64_t fcc0:2;		// Floating-Point condtion codes
+                uint64_t :1;		// Reserved bits
+                uint64_t qne:1;			// Deferred trap queue not empty
+                                                // with no queue, it should read 0
+                uint64_t ftt:3;			// Floating-Point trap type
+                uint64_t ver:3;			// Version (of the FPU)
+                uint64_t :2;		// Reserved bits
+                uint64_t ns:1;			// Nonstandard floating point
+                union
+                {
+                    uint64_t tem:5;			// Trap Enable Mask
+                    struct
+                    {
+                        uint64_t nxm:1;		// Inexact
+                        uint64_t dzm:1;		// Divide by zero
+                        uint64_t ufm:1;		// Underflow
+                        uint64_t ofm:1;		// Overflow
+                        uint64_t nvm:1;		// Invalid operand
+                    } temFields;
+                };
+                uint64_t :2;		// Reserved bits
+                uint64_t rd:2;			// Rounding direction
+                uint64_t fcc1:2;		// Floating-Point condition codes
+                uint64_t fcc2:2;		// Floating-Point condition codes
+                uint64_t fcc3:2;		// Floating-Point condition codes
+                uint64_t :26;		// Reserved bits
+            } fsrFields;
+        };
+        union
+        {
+            uint8_t		fprs;	// Floating-Point Register State
+            struct
+            {
+                uint8_t dl:1;		// Dirty lower
+                uint8_t du:1;		// Dirty upper
+                uint8_t fef:1;		// FPRS enable floating-Point
+            } fprsFields;
+        };
+
+      public:
+
+        void reset()
+        {
+            pstateFields.pef = 0; //No FPU
+            //pstateFields.pef = 1; //FPU
+#if FULL_SYSTEM
+            //For SPARC, when a system is first started, there is a power
+            //on reset Trap which sets the processor into the following state.
+            //Bits that aren't set aren't defined on startup.
+            tl = MaxTL;
+            tt[tl] = PowerOnReset.trapType();
+            pstateFields.mm = 0; //Total Store Order
+            pstateFields.red = 1; //Enter RED_State
+            pstateFields.am = 0; //Address Masking is turned off
+            pstateFields.priv = 1; //Processor enters privileged mode
+            pstateFields.ie = 0; //Interrupts are disabled
+            pstateFields.ag = 1; //Globals are replaced with alternate globals
+            pstateFields.tle = 0; //Big Endian mode for traps
+            pstateFields.cle = 0; //Big Endian mode for non-traps
+            tickFields.npt = 1; //The TICK register is unreadable by
+                                //non-priveleged software
+#else
+/*	    //This sets up the initial state of the processor for usermode processes
+            pstateFields.priv = 0; //Process runs in user mode
+            pstateFields.ie = 1; //Interrupts are enabled
+            fsrFields.rd = 0; //Round to nearest
+            fsrFields.tem = 0; //Floating point traps not enabled
+            fsrFields.ns = 0; //Non standard mode off
+            fsrFields.qne = 0; //Floating point queue is empty
+            fsrFields.aexc = 0; //No accrued exceptions
+            fsrFields.cexc = 0; //No current exceptions
+
+            //Register window management registers
+            otherwin = 0; //No windows contain info from other programs
+            canrestore = 0; //There are no windows to pop
+            cansave = MaxTL - 2; //All windows are available to save into
+            cleanwin = MaxTL;*/
+#endif
+        }
+
+        MiscRegFile()
+        {
+            reset();
+        }
+
+        MiscReg readReg(int miscReg);
+
+        MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
+
+        Fault setReg(int miscReg, const MiscReg &val);
+
+        Fault setRegWithEffect(int miscReg,
+                const MiscReg &val, ExecContext * xc);
+
+        void serialize(std::ostream & os);
+
+        void unserialize(Checkpoint * cp, const std::string & section);
+
+        void copyMiscRegs(ExecContext * xc);
+    };
+
+    typedef union
+    {
+        IntReg  intreg;
+        FloatReg   fpreg;
+        MiscReg ctrlreg;
+    } AnyReg;
+
+    class RegFile
+    {
+      protected:
+        Addr pc;		// Program Counter
+        Addr npc;		// Next Program Counter
+        Addr nnpc;
+
+      public:
+        Addr readPC()
+        {
+            return pc;
+        }
+
+        void setPC(Addr val)
+        {
+            pc = val;
+        }
+
+        Addr readNextPC()
+        {
+            return npc;
+        }
+
+        void setNextPC(Addr val)
+        {
+            npc = val;
+        }
+
+        Addr readNextNPC()
+        {
+            return nnpc;
+        }
+
+        void setNextNPC(Addr val)
+        {
+            nnpc = val;
+        }
+
+      protected:
+        IntRegFile intRegFile;		// integer register file
+        FloatRegFile floatRegFile;	// floating point register file
+        MiscRegFile miscRegFile;	// control register file
+
+      public:
+
+        void clear()
+        {
+            intRegFile.clear();
+            floatRegFile.clear();
+        }
+
+        int flattenIntIndex(int reg)
+        {
+            return intRegFile.flattenIndex(reg);
+        }
+
+        MiscReg readMiscReg(int miscReg)
+        {
+            return miscRegFile.readReg(miscReg);
+        }
+
+        MiscReg readMiscRegWithEffect(int miscReg,
+                Fault &fault, ExecContext *xc)
+        {
+            return miscRegFile.readRegWithEffect(miscReg, fault, xc);
+        }
+
+        Fault setMiscReg(int miscReg, const MiscReg &val)
+        {
+            return miscRegFile.setReg(miscReg, val);
+        }
+
+        Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
+                ExecContext * xc)
+        {
+            return miscRegFile.setRegWithEffect(miscReg, val, xc);
+        }
+
+        FloatReg readFloatReg(int floatReg, int width)
+        {
+            return floatRegFile.readReg(floatReg, width);
+        }
+
+        FloatReg readFloatReg(int floatReg)
+        {
+            //Use the "natural" width of a single float
+            return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
+        }
+
+        FloatRegBits readFloatRegBits(int floatReg, int width)
+        {
+            return floatRegFile.readRegBits(floatReg, width);
+        }
+
+        FloatRegBits readFloatRegBits(int floatReg)
+        {
+            //Use the "natural" width of a single float
+            return floatRegFile.readRegBits(floatReg,
+                    FloatRegFile::SingleWidth);
+        }
+
+        Fault setFloatReg(int floatReg, const FloatReg &val, int width)
+        {
+            return floatRegFile.setReg(floatReg, val, width);
+        }
+
+        Fault setFloatReg(int floatReg, const FloatReg &val)
+        {
+            //Use the "natural" width of a single float
+            return setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
+        }
+
+        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+        {
+            return floatRegFile.setRegBits(floatReg, val, width);
+        }
+
+        Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
+        {
+            //Use the "natural" width of a single float
+            return floatRegFile.setRegBits(floatReg, val,
+                    FloatRegFile::SingleWidth);
+        }
+
+        IntReg readIntReg(int intReg)
+        {
+            return intRegFile.readReg(intReg);
+        }
+
+        Fault setIntReg(int intReg, const IntReg &val)
+        {
+            return intRegFile.setReg(intReg, val);
+        }
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+
+      public:
+
+        enum ContextParam
+        {
+            CONTEXT_CWP,
+            CONTEXT_GLOBALS
+        };
+
+        union ContextVal
+        {
+            MiscReg reg;
+            bool altGlobals;
+        };
+
+        void changeContext(ContextParam param, ContextVal val)
+        {
+            switch(param)
+            {
+              case CONTEXT_CWP:
+                intRegFile.setCWP(val.reg);
+                break;
+              case CONTEXT_GLOBALS:
+                intRegFile.setAltGlobals(val.altGlobals);
+                break;
+              default:
+                panic("Tried to set illegal context parameter in the SPARC regfile.\n");
+            }
+        }
+    };
+
+    void copyRegs(ExecContext *src, ExecContext *dest);
+
+    void copyMiscRegs(ExecContext *src, ExecContext *dest);
+
+} // namespace SparcISA
+
+#endif