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author | Gabe Black <gblack@eecs.umich.edu> | 2010-11-11 02:03:58 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-11-11 02:03:58 -0800 |
commit | cdc585e0e8ceb305de83053c488ba041367b7cd6 (patch) | |
tree | ea3342231f3fdcbe52e3603294bfc46f072aaef7 /src/arch/sparc/registers.hh | |
parent | 0b7967d606cdda184df8df1446852e4aac93331d (diff) | |
download | gem5-cdc585e0e8ceb305de83053c488ba041367b7cd6.tar.xz |
SPARC: Clean up some historical style issues.
Diffstat (limited to 'src/arch/sparc/registers.hh')
-rw-r--r-- | src/arch/sparc/registers.hh | 61 |
1 files changed, 31 insertions, 30 deletions
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh index cf9f54b59..bb0f2bb89 100644 --- a/src/arch/sparc/registers.hh +++ b/src/arch/sparc/registers.hh @@ -39,42 +39,43 @@ namespace SparcISA { - using SparcISAInst::MaxInstSrcRegs; - using SparcISAInst::MaxInstDestRegs; - typedef uint64_t IntReg; - typedef uint64_t MiscReg; - typedef float FloatReg; - typedef uint32_t FloatRegBits; - typedef union - { - IntReg intReg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; +using SparcISAInst::MaxInstSrcRegs; +using SparcISAInst::MaxInstDestRegs; - typedef uint16_t RegIndex; +typedef uint64_t IntReg; +typedef uint64_t MiscReg; +typedef float FloatReg; +typedef uint32_t FloatRegBits; +typedef union +{ + IntReg intReg; + FloatReg fpreg; + MiscReg ctrlreg; +} AnyReg; + +typedef uint16_t RegIndex; - // These enumerate all the registers for dependence tracking. - enum DependenceTags { - FP_Base_DepTag = 32*3+9, - Ctrl_Base_DepTag = FP_Base_DepTag + 64, - Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs - }; +// These enumerate all the registers for dependence tracking. +enum DependenceTags { + FP_Base_DepTag = 32*3+9, + Ctrl_Base_DepTag = FP_Base_DepTag + 64, + Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs +}; - // semantically meaningful register indices - const int ZeroReg = 0; // architecturally meaningful - // the rest of these depend on the ABI - const int ReturnAddressReg = 31; // post call, precall is 15 - const int ReturnValueReg = 8; // Post return, 24 is pre-return. - const int StackPointerReg = 14; - const int FramePointerReg = 30; +// semantically meaningful register indices +const int ZeroReg = 0; // architecturally meaningful +// the rest of these depend on the ABI +const int ReturnAddressReg = 31; // post call, precall is 15 +const int ReturnValueReg = 8; // Post return, 24 is pre-return. +const int StackPointerReg = 14; +const int FramePointerReg = 30; - // Some OS syscall use a second register (o1) to return a second value - const int SyscallPseudoReturnReg = 9; +// Some OS syscall use a second register (o1) to return a second value +const int SyscallPseudoReturnReg = 9; - const int NumIntArchRegs = 32; - const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; +const int NumIntArchRegs = 32; +const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; } // namespace SparcISA |