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authorGabe Black <gabeblack@google.com>2018-10-12 17:48:48 -0700
committerGabe Black <gabeblack@google.com>2018-11-05 23:42:51 +0000
commitf3e17ca77a167ece1972ba73af1c63a85acf9ee8 (patch)
tree63cee0bf28ff00c85e5bc0bec5a3aa4dbe0f7ea6 /src/arch/sparc/registers.hh
parent9dbc9bb4f2b49cfa0d9f1cf844929896c27a2d27 (diff)
downloadgem5-f3e17ca77a167ece1972ba73af1c63a85acf9ee8.tar.xz
sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.
These types aren't used by the ISA itself since they're defined to be particular primitive types in the ISA description. This just affects code outside of the ISA which work with those types of registers. Change-Id: I4f62ab8fe04184cc23845090c82b250145a71747 Reviewed-on: https://gem5-review.googlesource.com/c/13616 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/sparc/registers.hh')
-rw-r--r--src/arch/sparc/registers.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index a7f4d2a15..b5acaeff1 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -47,8 +47,8 @@ using SparcISAInst::MaxMiscDestRegs;
typedef uint64_t IntReg;
typedef uint64_t MiscReg;
-typedef float FloatReg;
-typedef uint32_t FloatRegBits;
+typedef double FloatReg;
+typedef uint64_t FloatRegBits;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;