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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-04-22 17:43:45 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-04-22 17:43:45 +0000 |
| commit | cea543576082ed860e8dae17519ace48e5b2c78a (patch) | |
| tree | 46f99fc9428d1c992331c3a4ef71ce9b394d8a25 /src/arch/sparc/sparc_traits.hh | |
| parent | f3a0abbecc3456147f1ca3e297a50ae4353316fd (diff) | |
| download | gem5-cea543576082ed860e8dae17519ace48e5b2c78a.tar.xz | |
Make the GSR into a renamed control register. It should be split into a renamed part and a control part for the different bitfields, but the renamed part is all that's actually used.
--HG--
extra : convert_revision : ffeb4f874bd4430255064f6e8bcb135309932ff8
Diffstat (limited to 'src/arch/sparc/sparc_traits.hh')
| -rw-r--r-- | src/arch/sparc/sparc_traits.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/sparc/sparc_traits.hh b/src/arch/sparc/sparc_traits.hh index d89ec1119..715c08c03 100644 --- a/src/arch/sparc/sparc_traits.hh +++ b/src/arch/sparc/sparc_traits.hh @@ -42,7 +42,7 @@ namespace SparcISA // Number of register windows, can legally be 3 to 32 const int NWindows = 8; //const int NumMicroIntRegs = 1; - const int NumMicroIntRegs = 8; + const int NumMicroIntRegs = 9; // const int NumRegularIntRegs = MaxGL * 8 + NWindows * 16; // const int NumMicroIntRegs = 1; |