diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-07 18:50:33 -0500 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-07 18:50:33 -0500 |
commit | ed22eb781dc7714c1b2ca17cf17824917e38319c (patch) | |
tree | 776fa030f78b810b4964334ddb81802adff6b6d1 /src/arch/sparc/tlb.cc | |
parent | 03be92f23b36ba69bfee179f97cd5af23c0f6e2c (diff) | |
download | gem5-ed22eb781dc7714c1b2ca17cf17824917e38319c.tar.xz |
get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add sparc error asi
src/arch/sparc/faults.cc:
put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
add sparc error register code that just does nothing
fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
fix implementation of HPSTATE write
src/cpu/exetrace.cc:
let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
add l2 error status register fake devices
--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
Diffstat (limited to 'src/arch/sparc/tlb.cc')
-rw-r--r-- | src/arch/sparc/tlb.cc | 30 |
1 files changed, 26 insertions, 4 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 3ac3e5c9c..c05434797 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -328,6 +328,8 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", vaddr, req->getSize()); + DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n", + pstate, hpstate, lsuIm, part_id); assert(req->getAsi() == ASI_IMPLICIT); @@ -360,7 +362,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) return new InstructionAccessException; } - if (lsuIm) { + if (!lsuIm) { e = lookup(req->getVaddr(), part_id, true); real = true; context = 0; @@ -416,7 +418,8 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) asi = (ASI)req->getAsi(); DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", vaddr, size, asi); - + DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n", + pstate, hpstate, lsuDm, part_id); if (asi == ASI_IMPLICIT) implicit = true; @@ -489,6 +492,8 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) goto handleScratchRegAccess; if (AsiIsQueue(asi)) goto handleQueueRegAccess; + if (AsiIsSparcError(asi)) + goto handleSparcErrorRegAccess; if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) panic("Accessing ASI %#X. Should we?\n", asi); @@ -560,6 +565,19 @@ handleQueueRegAccess: } goto regAccessOk; +handleSparcErrorRegAccess: + if (!hpriv) { + if (priv) { + writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); + return new DataAccessException; + } else { + writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); + return new PrivilegedAction; + } + } + goto regAccessOk; + + regAccessOk: handleMmuRegAccess: DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); @@ -675,7 +693,7 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) Addr va = pkt->getAddr(); ASI asi = (ASI)pkt->req->getAsi(); - DPRINTF(IPR, "Memory Mapped IPR Write: asi=#%X a=%#x d=%#X\n", + DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", (uint32_t)asi, va, data); switch (asi) { @@ -696,7 +714,7 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) } break; case ASI_QUEUE: - assert(mbits(va,13,6) == va); + assert(mbits(data,13,6) == data); tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + (va >> 4) - 0x3c, data); break; @@ -748,6 +766,10 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) assert(va == 0); tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); break; + case ASI_SPARC_ERROR_EN_REG: + case ASI_SPARC_ERROR_STATUS_REG: + warn("Ignoring write to SPARC ERROR regsiter\n"); + break; case ASI_HYP_SCRATCHPAD: case ASI_SCRATCHPAD: tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); |