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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-08 21:49:13 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-08 21:49:13 -0500 |
| commit | 1158da37fb7a60fcb1f13318d08d11c2df287c99 (patch) | |
| tree | 910204150993ece7b67ad4264d50acf02889c23f /src/arch/sparc/tlb.cc | |
| parent | 027dfa01e6ca7e9feed334eef5fab7cfbbb18c52 (diff) | |
| download | gem5-1158da37fb7a60fcb1f13318d08d11c2df287c99.tar.xz | |
Panic if any CMT registers are accessed
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add CMT ASI registers
src/arch/sparc/tlb.cc:
Panic if any of the CMT registers are being accessed
--HG--
extra : convert_revision : b9a94281e2074a576ac21d042b756950d509e758
Diffstat (limited to 'src/arch/sparc/tlb.cc')
| -rw-r--r-- | src/arch/sparc/tlb.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index c39969769..09266fd6e 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -693,6 +693,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) if (AsiIsPartialStore(asi)) panic("Partial Store ASIs not supported\n"); + if (AsiIsCmt(asi)) + panic("Cmt ASI registers not implmented\n"); + if (AsiIsInterrupt(asi)) goto handleIntRegAccess; if (AsiIsMmu(asi)) |