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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-22 16:11:49 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-22 16:11:49 -0500 |
| commit | e347b49a4edfe89ed5c5352b6c1b93b69ab00134 (patch) | |
| tree | eed2c6072e1a23673bd2674ffc243a22a05ee4c5 /src/arch/sparc/tlb.cc | |
| parent | a7072c19dbd6273920a90a4ec5fa013531316287 (diff) | |
| download | gem5-e347b49a4edfe89ed5c5352b6c1b93b69ab00134.tar.xz | |
use writeTagAccess() function to unify writing of Tag access registers
Fix extracting of secondary context to shove into tag access register
properly sign extend va from 59 bits to 63 (SPARC VA hole)
--HG--
extra : convert_revision : 5d0c2b4db63338c31b2d29b4bb68f39e1d4f4c7b
Diffstat (limited to 'src/arch/sparc/tlb.cc')
| -rw-r--r-- | src/arch/sparc/tlb.cc | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 61445954f..e3ac26612 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -415,6 +415,9 @@ TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, void TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) { + DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", + va, context, mbits(va, 63,13) | mbits(context,12,0)); + tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); } @@ -537,8 +540,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) } if (e == NULL || !e->valid) { - tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, - vaddr & ~BytesInPageMask | context); + writeTagAccess(tc, vaddr, context); if (real) return new InstructionRealTranslationMiss; else @@ -611,7 +613,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) int part_id = bits(tlbdata,15,8); int tl = bits(tlbdata,18,16); int pri_context = bits(tlbdata,47,32); - int sec_context = bits(tlbdata,47,32); + int sec_context = bits(tlbdata,63,48); bool real = false; ContextType ct = Primary; @@ -723,8 +725,7 @@ continueDtbFlow: e = lookup(vaddr, part_id, real, context); if (e == NULL || !e->valid) { - tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, - vaddr & ~BytesInPageMask | context); + writeTagAccess(tc, vaddr, context); DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); if (real) return new DataRealTranslationMiss; @@ -1115,6 +1116,7 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); break; case 0x30: + sext<59>(bits(data, 59,0)); tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); break; default: @@ -1189,6 +1191,7 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); break; case 0x30: + sext<59>(bits(data, 59,0)); tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); break; case 0x80: |