Implement Niagara I/O interface and rework interrupts

configs/common/FSConfig.py:
    Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
    get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
    Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Add InterruptVector type
src/arch/sparc/interrupts.hh:
    rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
    Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
    add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
    Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
    InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
    Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
    Add checkSoftInt to check if a softint needs to be posted
    Check that a tickCompare isn't scheduled before scheduling one
    Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
    Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
    get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
    Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
    add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
    update config.ini/out for intrcntrl not having a cpu pointer anymore

--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd

1 files changed, 42 insertions, 4 deletions

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 2dca6d5e7..41d55158e 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -40,6 +40,7 @@
 #include "mem/packet_access.hh"
 #include "mem/request.hh"
 #include "sim/builder.hh"
+#include "sim/system.hh"
 
 /* @todo remove some of the magic constants.  -- ali
  * */
@@ -691,9 +692,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 
         if (AsiIsPartialStore(asi))
             panic("Partial Store ASIs not supported\n");
-        if (AsiIsInterrupt(asi))
-            panic("Interrupt ASIs not supported\n");
 
+        if (AsiIsInterrupt(asi))
+            goto handleIntRegAccess;
         if (AsiIsMmu(asi))
             goto handleMmuRegAccess;
         if (AsiIsScratchPad(asi))
@@ -793,7 +794,25 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
                   vaddr & e->pte.size()-1);
     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
     return NoFault;
+
     /** Normal flow ends here. */
+handleIntRegAccess:
+    if (!hpriv) {
+        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
+        if (priv)
+            return new DataAccessException;
+         else
+            return new PrivilegedAction;
+    }
+
+    if (asi == ASI_SWVR_UDB_INTR_W && !write ||
+                    asi == ASI_SWVR_UDB_INTR_R && write) {
+        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
+        return new DataAccessException;
+    }
+
+    goto regAccessOk;
+
 
 handleScratchRegAccess:
     if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
@@ -988,7 +1007,14 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
                 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1),
                 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)));
         break;
-
+      case ASI_SWVR_INTR_RECEIVE:
+        pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
+        break;
+      case ASI_SWVR_UDB_INTR_R:
+        temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
+        tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
+        pkt->set(temp);
+        break;
       default:
 doMmuReadError:
         panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
@@ -1222,7 +1248,19 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
             panic("Invalid type for IMMU demap\n");
         }
         break;
-      default:
+       case ASI_SWVR_INTR_RECEIVE:
+        int msb;
+        // clear all the interrupts that aren't set in the write
+        while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) {
+            msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data);
+            tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
+        }
+        break;
+      case ASI_SWVR_UDB_INTR_W:
+            tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
+            post_interrupt(bits(data,5,0),0);
+        break;
+ default:
 doMmuWriteError:
         panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
             (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);