diff options
| author | Nathan Binkert <nate@binkert.org> | 2008-10-21 07:12:53 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2008-10-21 07:12:53 -0700 |
| commit | 9836d81c2bba97e36c43ca22feee1d51a12ce6ac (patch) | |
| tree | eaa352df03cfe58d315e975bbe2a6384c801f221 /src/arch/sparc/tlb.cc | |
| parent | aac93b7d0ce5e8e0241c7299b49cc59a9d095f3e (diff) | |
| download | gem5-9836d81c2bba97e36c43ca22feee1d51a12ce6ac.tar.xz | |
style: Use the correct m5 style for things relating to interrupts.
Diffstat (limited to 'src/arch/sparc/tlb.cc')
| -rw-r--r-- | src/arch/sparc/tlb.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 61f0985db..b6a450ffe 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -1021,7 +1021,7 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) dynamic_cast<SparcISA::Interrupts *>( tc->getCpuPtr()->getInterruptController()); temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); - tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp); + tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp); pkt->set(temp); } break; @@ -1268,15 +1268,15 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) SparcISA::Interrupts * interrupts = dynamic_cast<SparcISA::Interrupts *>( tc->getCpuPtr()->getInterruptController()); - while(interrupts->get_vec(IT_INT_VEC) & data) { + while (interrupts->get_vec(IT_INT_VEC) & data) { msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); - tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb); + tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb); } } break; case ASI_SWVR_UDB_INTR_W: tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> - post_interrupt(bits(data,5,0),0); + postInterrupt(bits(data, 5, 0), 0); break; default: doMmuWriteError: |