Add support for mmapped iprs to atomic cpu

src/arch/SConscript:
    add mmaped_ipr.hh to switch headers
src/arch/sparc/asi.hh:
    make ASI_IMPLICT=0 so by default nothing needs to be done
src/arch/sparc/miscregfile.hh:
    miscregfile no longer needs to include asi.hh
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
    implement panic instructions for mmaped ipr reads
src/cpu/simple/atomic.cc:
    add check for mmaped iprs and handle them if it exists
src/mem/request.hh:
    allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits

--HG--
extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115

1 files changed, 21 insertions, 3 deletions

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 9b7943ed9..5fde4d36d 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -508,13 +508,31 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
     req->setPaddr(e->pte.paddr() & ~e->pte.size() |
                   req->getVaddr() & e->pte.size());
     return NoFault;
-    /*** End of normal Path ***/
+    /** Normal flow ends here. */
 
-handleMmuRegAccess:
 handleScratchRegAccess:
-    panic("How are we ever going to deal with this?\n");
+    if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
+        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
+        return new DataAccessException;
+    }
+handleMmuRegAccess:
+    req->setMmapedIpr(true);
+    req->setPaddr(req->getVaddr());
+    return NoFault;
 };
 
+Tick
+DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
+{
+    panic("need to implement DTB::doMmuRegRead()\n");
+}
+
+Tick
+DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
+{
+    panic("need to implement DTB::doMmuRegWrite()\n");
+}
+
 void
 TLB::serialize(std::ostream &os)
 {