diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
| commit | 537239b278f7b8171d2eb09ef7f99c332266c48f (patch) | |
| tree | 31984b63cc542f0a57ca96262477575ab0130c09 /src/arch/sparc/tlb.cc | |
| parent | f738afb865cd82487d6300259d6e87fb50660d2a (diff) | |
| download | gem5-537239b278f7b8171d2eb09ef7f99c332266c48f.tar.xz | |
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
Diffstat (limited to 'src/arch/sparc/tlb.cc')
| -rw-r--r-- | src/arch/sparc/tlb.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 12891e2b3..edc9d37a9 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -535,7 +535,11 @@ ITB::translate(RequestPtr &req, ThreadContext *tc) if (real) return new InstructionRealTranslationMiss; else +#if FULL_SYSTEM return new FastInstructionAccessMMUMiss; +#else + return new FastInstructionAccessMMUMiss(req->getVaddr()); +#endif } // were not priviledged accesing priv page @@ -744,7 +748,11 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) if (real) return new DataRealTranslationMiss; else +#if FULL_SYSTEM return new FastDataAccessMMUMiss; +#else + return new FastDataAccessMMUMiss(req->getVaddr()); +#endif } @@ -853,6 +861,8 @@ handleMmuRegAccess: return NoFault; }; +#if FULL_SYSTEM + Tick DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) { @@ -1275,6 +1285,8 @@ doMmuWriteError: return tc->getCpuPtr()->cycles(1); } +#endif + void DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) { |