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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
| commit | a5c4eb3de9deb3a71a6a5230a25ff5962e584980 (patch) | |
| tree | 874b659c6a5eaa1316cde9eb82ec7d08badf638a /src/arch/sparc/tlb.cc | |
| parent | e255fa053f8d105de8d188077a318124a3aad9ce (diff) | |
| download | gem5-a5c4eb3de9deb3a71a6a5230a25ff5962e584980.tar.xz | |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
Diffstat (limited to 'src/arch/sparc/tlb.cc')
| -rw-r--r-- | src/arch/sparc/tlb.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index c0c28f952..b4a761293 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -1022,7 +1022,7 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) { SparcISA::Interrupts * interrupts = dynamic_cast<SparcISA::Interrupts *>( - tc->getCpuPtr()->getInterruptController()); + tc->getCpuPtr()->getInterruptController(0)); pkt->set(interrupts->get_vec(IT_INT_VEC)); } break; @@ -1030,9 +1030,9 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) { SparcISA::Interrupts * interrupts = dynamic_cast<SparcISA::Interrupts *>( - tc->getCpuPtr()->getInterruptController()); + tc->getCpuPtr()->getInterruptController(0)); temp = findMsbSet(interrupts->get_vec(IT_INT_VEC)); - tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp); + tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp); pkt->set(temp); } break; @@ -1278,16 +1278,16 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) // clear all the interrupts that aren't set in the write SparcISA::Interrupts * interrupts = dynamic_cast<SparcISA::Interrupts *>( - tc->getCpuPtr()->getInterruptController()); + tc->getCpuPtr()->getInterruptController(0)); while (interrupts->get_vec(IT_INT_VEC) & data) { msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data); - tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb); + tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb); } } break; case ASI_SWVR_UDB_INTR_W: tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> - postInterrupt(bits(data, 5, 0), 0); + postInterrupt(0, bits(data, 5, 0), 0); break; default: doMmuWriteError: |