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| author | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-18 03:37:52 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-18 03:37:52 -0500 |
| commit | 6841f863c5dee6ce2028ba647254ec9ad27a57fd (patch) | |
| tree | 816fc67716d4fc04ea85e1af77e64036c119539a /src/arch/sparc/tlb.cc | |
| parent | e65544b88b86c48bf8f65bd2ebc895a4ce90c6cc (diff) | |
| download | gem5-6841f863c5dee6ce2028ba647254ec9ad27a57fd.tar.xz | |
move the twinx loads to the correct opcode and add asis 0x24 and 0x27
Make the TLB ok to translate QUAD_LDD
src/arch/sparc/isa/decoder.isa:
move the twinx loads to the correct opcode.
src/arch/sparc/tlb.cc:
Make QUAD_LDD asi ok to execute
--HG--
extra : convert_revision : 2a44d1c9e4edb627079fc05776c28d918c8508ce
Diffstat (limited to 'src/arch/sparc/tlb.cc')
| -rw-r--r-- | src/arch/sparc/tlb.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 675287d18..1eb3aa53b 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -575,6 +575,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) if (write && asi == ASI_LDTX_P) // block init store (like write hint64) goto continueDtbFlow; + if (!write && asi == ASI_QUAD_LDD) + goto continueDtbFlow; + if (AsiIsTwin(asi)) panic("Twin ASIs not supported\n"); if (AsiIsPartialStore(asi)) |