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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-17 13:09:26 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-17 13:09:26 -0500 |
| commit | 8173a05eaf533fd9229c41c106dce0e532c49b0b (patch) | |
| tree | 4f25e6cea90009cea4bb7478028c1c3c51d13087 /src/arch/sparc/tlb.cc | |
| parent | 64528df38d7484591ae27bb2a2252fc1bccd4e9a (diff) | |
| download | gem5-8173a05eaf533fd9229c41c106dce0e532c49b0b.tar.xz | |
Implement reading writing of sync fault status register and address register
--HG--
extra : convert_revision : c2f60e49683446bcc3afdf911da172de0422b8ad
Diffstat (limited to 'src/arch/sparc/tlb.cc')
| -rw-r--r-- | src/arch/sparc/tlb.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 0935cee4e..e8b0a933b 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -876,6 +876,9 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); break; + case 0x18: + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR)); + break; case 0x30: pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); break; @@ -889,6 +892,12 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); break; + case 0x18: + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR)); + break; + case 0x20: + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR)); + break; case 0x30: pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); break; @@ -1070,6 +1079,9 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) break; case ASI_IMMU: switch (va) { + case 0x18: + tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); + break; case 0x30: tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); break; @@ -1141,6 +1153,9 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) break; case ASI_DMMU: switch (va) { + case 0x18: + tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); + break; case 0x30: tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); break; |