diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
| commit | 537239b278f7b8171d2eb09ef7f99c332266c48f (patch) | |
| tree | 31984b63cc542f0a57ca96262477575ab0130c09 /src/arch/sparc/tlb.hh | |
| parent | f738afb865cd82487d6300259d6e87fb50660d2a (diff) | |
| download | gem5-537239b278f7b8171d2eb09ef7f99c332266c48f.tar.xz | |
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
Diffstat (limited to 'src/arch/sparc/tlb.hh')
| -rw-r--r-- | src/arch/sparc/tlb.hh | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index e1111db8d..d35a6e096 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -34,6 +34,7 @@ #include "arch/sparc/asi.hh" #include "arch/sparc/tlb_map.hh" #include "base/misc.hh" +#include "config/full_system.hh" #include "mem/request.hh" #include "sim/faults.hh" #include "sim/sim_object.hh" @@ -46,6 +47,12 @@ namespace SparcISA class TLB : public SimObject { +#if !FULL_SYSTEM + //These faults need to be able to populate the tlb in SE mode. + friend class FastInstructionAccessMMUMiss; + friend class FastDataAccessMMUMiss; +#endif + //TLB state protected: uint64_t c0_tsb_ps0; @@ -183,8 +190,10 @@ class DTB : public TLB } Fault translate(RequestPtr &req, ThreadContext *tc, bool write); +#if FULL_SYSTEM Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); +#endif void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); // Checkpointing |