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author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
commit | 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 (patch) | |
tree | 736bc7ea34184fb103fd836e67672521193602a7 /src/arch/sparc/tlb.hh | |
parent | f3ba6d20f6070c30418866e627e2418f39b433dd (diff) | |
download | gem5-2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0.tar.xz |
Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
Diffstat (limited to 'src/arch/sparc/tlb.hh')
-rw-r--r-- | src/arch/sparc/tlb.hh | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index 35ff08b43..0d42e2c97 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -31,5 +31,33 @@ #ifndef __ARCH_SPARC_TLB_HH__ #define __ARCH_SPARC_TLB_HH__ +#include "sim/faults.hh" + +class ThreadContext; + +namespace SparcISA +{ + class TLB + { + }; + + class ITB : public TLB + { + public: + Fault translate(RequestPtr &req, ThreadContext *tc) const + { + return NoFault; + } + }; + + class DTB : public TLB + { + public: + Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const + { + return NoFault; + } + }; +} #endif // __ARCH_SPARC_TLB_HH__ |