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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 23:38:51 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-02-26 23:38:51 -0500 |
| commit | 8b4796a367ec21d294f7318343e5bb9d7e07a53e (patch) | |
| tree | 584199359a9a7aa3c7d842164b677d1a1e94a1f1 /src/arch/sparc/tlb.hh | |
| parent | 7bde0285e50e3903e38dd9e6fd59ea4a98f41079 (diff) | |
| download | gem5-8b4796a367ec21d294f7318343e5bb9d7e07a53e.tar.xz | |
TLB: Make a TLB base class and put a virtual demapPage function in it.
--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
Diffstat (limited to 'src/arch/sparc/tlb.hh')
| -rw-r--r-- | src/arch/sparc/tlb.hh | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index b38ee15dc..2f7d08320 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -39,7 +39,7 @@ #include "params/SparcDTB.hh" #include "params/SparcITB.hh" #include "sim/faults.hh" -#include "sim/sim_object.hh" +#include "sim/tlb.hh" class ThreadContext; class Packet; @@ -47,7 +47,7 @@ class Packet; namespace SparcISA { -class TLB : public SimObject +class TLB : public BaseTLB { #if !FULL_SYSTEM //These faults need to be able to populate the tlb in SE mode. @@ -152,6 +152,11 @@ class TLB : public SimObject typedef SparcTLBParams Params; TLB(const Params *p); + void demapPage(Addr vaddr, uint64_t asn) + { + panic("demapPage(Addr) is not implemented.\n"); + } + void dumpAll(); // Checkpointing |