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author | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-09 18:00:40 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-12-09 18:00:40 -0500 |
commit | 81a00fdcfef4ecffd57a909db67ca0ff3b99de3a (patch) | |
tree | a80cc38ae0827b41f66560750606bb9061955481 /src/arch/sparc/tlb.hh | |
parent | ed22eb781dc7714c1b2ca17cf17824917e38319c (diff) | |
download | gem5-81a00fdcfef4ecffd57a909db67ca0ff3b99de3a.tar.xz |
Allocate the correct number of global registers
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
Diffstat (limited to 'src/arch/sparc/tlb.hh')
-rw-r--r-- | src/arch/sparc/tlb.hh | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index 2df4fe4c8..8a4ccd69f 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -84,7 +84,7 @@ class TLB : public SimObject /** Insert a PTE into the TLB. */ void insert(Addr vpn, int partition_id, int context_id, bool real, - const PageTableEntry& PTE); + const PageTableEntry& PTE, int entry = -1); /** Given an entry id, read that tlb entries' tag. */ uint64_t TagRead(int entry); @@ -114,9 +114,13 @@ class TLB : public SimObject void TLB::clearUsedBits(); + void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context); + public: TLB(const std::string &name, int size); + void dumpAll(); + // Checkpointing virtual void serialize(std::ostream &os); virtual void unserialize(Checkpoint *cp, const std::string §ion); @@ -133,6 +137,8 @@ class ITB : public TLB private: void writeSfsr(ThreadContext *tc, bool write, ContextType ct, bool se, FaultTypes ft, int asi); + void writeTagAccess(ThreadContext *tc, Addr va, int context); + friend class DTB; }; class DTB : public TLB @@ -149,6 +155,8 @@ class DTB : public TLB private: void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, bool se, FaultTypes ft, int asi); + void writeTagAccess(ThreadContext *tc, Addr va, int context); + }; |