CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.

1 files changed, 7 insertions, 2 deletions

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index d563772e6..4fe532d4a 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -177,7 +177,9 @@ class ITB : public TLB
         cacheEntry = NULL;
     }
 
-    Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation);
   private:
     void writeSfsr(bool write, ContextType ct,
             bool se, FaultTypes ft, int asi);
@@ -199,7 +201,10 @@ class DTB : public TLB
         cacheEntry[1] = NULL;
     }
 
-    Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
+    Fault translateAtomic(RequestPtr req,
+            ThreadContext *tc, bool write=false);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation, bool write=false);
 #if FULL_SYSTEM
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);