diff options
| author | Steve Reinhardt <stever@gmail.com> | 2008-02-27 18:18:56 -0500 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2008-02-27 18:18:56 -0500 |
| commit | 19dfde231764855df58c2ac183c012953daa32c6 (patch) | |
| tree | 5d03d25a5e3c9b3b687bac0eb53fc6e19c5e1e67 /src/arch/sparc/tlb.hh | |
| parent | 2f41006e448a6af11dcf36b7804edd91c7710bda (diff) | |
| parent | 8fb74c238cbf7a394d5d547dea987e35eddfca79 (diff) | |
| download | gem5-19dfde231764855df58c2ac183c012953daa32c6.tar.xz | |
Automated merge with ssh://daystrom.m5sim.org//repo/m5
--HG--
extra : convert_revision : f4bcd342e7abb86ca83840b723e6ab0b861ecf5b
Diffstat (limited to 'src/arch/sparc/tlb.hh')
| -rw-r--r-- | src/arch/sparc/tlb.hh | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index b38ee15dc..2f7d08320 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -39,7 +39,7 @@ #include "params/SparcDTB.hh" #include "params/SparcITB.hh" #include "sim/faults.hh" -#include "sim/sim_object.hh" +#include "sim/tlb.hh" class ThreadContext; class Packet; @@ -47,7 +47,7 @@ class Packet; namespace SparcISA { -class TLB : public SimObject +class TLB : public BaseTLB { #if !FULL_SYSTEM //These faults need to be able to populate the tlb in SE mode. @@ -152,6 +152,11 @@ class TLB : public SimObject typedef SparcTLBParams Params; TLB(const Params *p); + void demapPage(Addr vaddr, uint64_t asn) + { + panic("demapPage(Addr) is not implemented.\n"); + } + void dumpAll(); // Checkpointing |