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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-11-11 02:03:58 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-11-11 02:03:58 -0800 |
| commit | cdc585e0e8ceb305de83053c488ba041367b7cd6 (patch) | |
| tree | ea3342231f3fdcbe52e3603294bfc46f072aaef7 /src/arch/sparc/types.hh | |
| parent | 0b7967d606cdda184df8df1446852e4aac93331d (diff) | |
| download | gem5-cdc585e0e8ceb305de83053c488ba041367b7cd6.tar.xz | |
SPARC: Clean up some historical style issues.
Diffstat (limited to 'src/arch/sparc/types.hh')
| -rw-r--r-- | src/arch/sparc/types.hh | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh index 122fd808f..b996be03c 100644 --- a/src/arch/sparc/types.hh +++ b/src/arch/sparc/types.hh @@ -37,16 +37,19 @@ namespace SparcISA { - typedef uint32_t MachInst; - typedef uint64_t ExtMachInst; - typedef GenericISA::DelaySlotUPCState<MachInst> PCState; +typedef uint32_t MachInst; +typedef uint64_t ExtMachInst; - typedef Twin64_t LargestRead; +typedef GenericISA::DelaySlotUPCState<MachInst> PCState; + +typedef Twin64_t LargestRead; + +struct CoreSpecific +{ + int core_type; +}; - struct CoreSpecific { - int core_type; - }; } #endif |