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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-22 21:55:43 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-22 21:55:43 -0500 |
| commit | 5f662d451ee8311c0f42eaf6ed6415b4d0f0f473 (patch) | |
| tree | 794652e4eb946d68aee64782806ce5482b493aba /src/arch/sparc/ua2005.cc | |
| parent | 3011fc63111735bc3de000f121661ee60631cb4c (diff) | |
| download | gem5-5f662d451ee8311c0f42eaf6ed6415b4d0f0f473.tar.xz | |
clean up fault code a little bit
simplify and make complete some asi checks
implement all the twin asis and remove panic checks on their use
soft int is supported, so we don't need to print writes to it
src/arch/sparc/asi.cc:
make AsiIsLittle() be all the little asis.
Speed up AsiIsTwin() a bit
src/arch/sparc/faults.cc:
clean up the do*Fault code.... Make it work like legion, in particular
pstate.priv is left alone, not set to 0 like the spec says
src/arch/sparc/isa/decoder.isa:
implement some more twin ASIs
src/arch/sparc/tlb.cc:
All the twin asis are implemented, no need to say their not supported anymore
src/arch/sparc/ua2005.cc:
softint is supported now, no more need to
--HG--
extra : convert_revision : aef2a1b93719235edff830a17a8ec52f23ec9f8b
Diffstat (limited to 'src/arch/sparc/ua2005.cc')
| -rw-r--r-- | src/arch/sparc/ua2005.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 6220e6dec..00a44275c 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -43,8 +43,6 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, /* Full system only ASRs */ case MISCREG_SOFTINT: setReg(miscReg, val);; - if (val != 0x10000 && val != 0) - warn("Writing to softint not really supported, writing: %#x\n", val); break; case MISCREG_SOFTINT_CLR: |