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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-10-09 23:48:27 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-10-09 23:48:27 -0700 |
| commit | 5bab52d56ddd482ae7eb1a6ae45d2a97fd457ca2 (patch) | |
| tree | 53445f377a4abb37031138786d3ac9ab1e91d84e /src/arch/sparc/ua2005.cc | |
| parent | 48b40cff650cb071b189826af2f2e1f78434f49b (diff) | |
| download | gem5-5bab52d56ddd482ae7eb1a6ae45d2a97fd457ca2.tar.xz | |
[mq]: sefssparcregfile.patch
Diffstat (limited to 'src/arch/sparc/ua2005.cc')
| -rw-r--r-- | src/arch/sparc/ua2005.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 67c17900b..70c8c18e6 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -207,12 +207,10 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) case MISCREG_HPSTATE: // T1000 spec says impl. dependent val must always be 1 setMiscRegNoEffect(miscReg, val | HPSTATE::id); -#if FULL_SYSTEM if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); else cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); -#endif break; case MISCREG_HTSTATE: setMiscRegNoEffect(miscReg, val); @@ -226,8 +224,10 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); // Time to go to sleep tc->suspend(); +#if FULL_SYSTEM if (tc->getKernelStats()) tc->getKernelStats()->quiesce(); +#endif } break; |