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authorGabe Black <gblack@eecs.umich.edu>2009-02-25 10:22:31 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-25 10:22:31 -0800
commit437b02884dedccc6f72f3e5d9c05d3a2dd6c6a2d (patch)
tree269dc7331610a9118bb884adf0c3fb39b40088a8 /src/arch/sparc/ua2005.cc
parent3b01535ec1ea6f51738675b3caf36e3f100ad128 (diff)
downloadgem5-437b02884dedccc6f72f3e5d9c05d3a2dd6c6a2d.tar.xz
ISA: Get rid of the get*RegName functions.
Diffstat (limited to 'src/arch/sparc/ua2005.cc')
-rw-r--r--src/arch/sparc/ua2005.cc21
1 files changed, 21 insertions, 0 deletions
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 2389c963d..880d2c3eb 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -35,6 +35,7 @@
#include "sim/system.hh"
using namespace SparcISA;
+using namespace std;
void
@@ -61,6 +62,26 @@ MiscRegFile::checkSoftInt(ThreadContext *tc)
}
}
+//These functions map register indices to names
+static inline string
+getMiscRegName(RegIndex index)
+{
+ static string miscRegName[NumMiscRegs] =
+ {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
+ "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
+ "stick", "stick_cmpr",
+ "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
+ "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
+ "wstate",*/ "gl",
+ "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
+ "hstick_cmpr",
+ "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
+ "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
+ "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
+ "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
+ "nresErrorHead", "nresErrorTail", "TlbData" };
+ return miscRegName[index];
+}
void
MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)