diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2010-11-11 02:03:58 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-11-11 02:03:58 -0800 |
| commit | cdc585e0e8ceb305de83053c488ba041367b7cd6 (patch) | |
| tree | ea3342231f3fdcbe52e3603294bfc46f072aaef7 /src/arch/sparc/ua2005.cc | |
| parent | 0b7967d606cdda184df8df1446852e4aac93331d (diff) | |
| download | gem5-cdc585e0e8ceb305de83053c488ba041367b7cd6.tar.xz | |
SPARC: Clean up some historical style issues.
Diffstat (limited to 'src/arch/sparc/ua2005.cc')
| -rw-r--r-- | src/arch/sparc/ua2005.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 95381db38..bd6497b25 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -63,7 +63,7 @@ ISA::checkSoftInt(ThreadContext *tc) } } -//These functions map register indices to names +// These functions map register indices to names static inline string getMiscRegName(RegIndex index) { @@ -267,7 +267,7 @@ ISA::readFSReg(int miscReg, ThreadContext * tc) return ULL(0x3e) << 48 | ULL(0x23) << 32 | ULL(0x20) << 24 | - //MaxGL << 16 | XXX For some reason legion doesn't set GL + // MaxGL << 16 | XXX For some reason legion doesn't set GL MaxTL << 8 | (NWindows -1) << 0; @@ -334,8 +334,9 @@ ISA::processSTickCompare(ThreadContext *tc) if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); } - } else + } else { cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1)); + } } void @@ -361,7 +362,8 @@ ISA::processHSTickCompare(ThreadContext *tc) setMiscReg(MISCREG_HINTP, 1, tc); } // Need to do something to cause interrupt to happen here !!! @todo - } else + } else { cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1)); + } } |