mostly implemented SOFTINT relevant interrupt stuff.

src/arch/sparc/interrupts.hh:
    add in thread_context.hh to get access to tc.
    get rid of stubs that don't make sense right now.
    implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
    softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
    add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
    implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.

--HG--
extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae

1 files changed, 14 insertions, 11 deletions

diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 32bc2a44b..c5188f405 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -41,18 +41,12 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         ThreadContext *tc)
 {
     int64_t time;
-    int oldLevel, newLevel;
     switch (miscReg) {
         /* Full system only ASRs */
         case MISCREG_SOFTINT:
           // Check if we are going to interrupt because of something
-          oldLevel = InterruptLevel(softint);
-          newLevel = InterruptLevel(val);
           setReg(miscReg, val);
-          if (newLevel > oldLevel)
-              ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
-              //tc->getCpuPtr()->checkInterrupts = true;
-          panic("SOFTINT not implemented\n");
+          tc->getCpuPtr()->checkInterrupts = true;
           break;
 
         case MISCREG_SOFTINT_CLR:
@@ -82,11 +76,17 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
               sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
           break;
 
+        case MISCREG_PSTATE:
+          if (val & ie && !(pstate & ie)) {
+              tc->getCpuPtr()->checkInterrupts = true;
+          }
+          setReg(miscReg, val);
+
         case MISCREG_PIL:
+          if (val < pil) {
+              tc->getCpuPtr()->checkInterrupts = true;
+          }
           setReg(miscReg, val);
-          //tc->getCpuPtr()->checkInterrupts;
-          // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
-          panic("PIL not implemented\n");
           break;
 
         case MISCREG_HVER:
@@ -109,13 +109,16 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
           break;
 
         case MISCREG_HPSTATE:
+          // T1000 spec says impl. dependent val must always be 1
+          setReg(miscReg, val | id);
+
         case MISCREG_HTSTATE:
         case MISCREG_STRAND_STS_REG:
           setReg(miscReg, val);
           break;
 
         default:
-          panic("Invalid write to FS misc register\n");
+          panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
     }
 }