Some support for handling block loads and stores and ASIs properly.

src/arch/sparc/isa/bitfields.isa:
    Added a field to retrieve the asi from the ExtMachInst
src/arch/sparc/isa/decoder.isa:
    Fixed up how the size of memory operations where handled, and use the new EXT_ASI bit field.
src/arch/sparc/isa/formats.isa:
    add includes for the new formats.
src/arch/sparc/isa/formats/basic.isa:
    Add a template for BasicDecodeWithMnemonic which is needed by the unimp format.
src/arch/sparc/isa/formats/mem.isa:
    Change around the memory format to figure out the memory access width on its own.
src/arch/sparc/isa/operands.isa:
    Added support for the operands of block loads/stores which are offset from Frd.
src/arch/sparc/utility.hh:
    Encoded the ASI into the ExtMachInst

--HG--
extra : convert_revision : 5c6026a07e3a919e738d27f78beb0faf6b060643

1 files changed, 11 insertions, 2 deletions

diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index f1c071148..796b6ba4c 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -33,12 +33,21 @@
 
 #include "arch/sparc/isa_traits.hh"
 #include "base/misc.hh"
+#include "cpu/thread_context.hh"
 
 namespace SparcISA
 {
     inline ExtMachInst
-    makeExtMI(MachInst inst, const Addr &pc) {
-        return ExtMachInst(inst);
+    makeExtMI(MachInst inst, ThreadContext * xc) {
+        ExtMachInst emi = (unsigned MachInst) inst;
+        //The I bit, bit 13, is used to figure out where the ASI
+        //should come from. Use that in the ExtMachInst. This is
+        //slightly redundant, but it removes the need to put a condition
+        //into all the execute functions
+        if(inst & (1 << 13))
+            emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI))
+                    << (sizeof(MachInst) * 8));
+        return emi;
     }
 
     inline bool isCallerSaveIntegerRegister(unsigned int reg) {