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authorRekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>2017-04-05 13:24:00 -0500
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-07-05 14:43:49 +0000
commit00da08902918da13fccc3f2266b7b2f5d0080708 (patch)
treeb495a0ceba7e073adca005cf84a7575d0aad5f27 /src/arch/sparc
parent0747a432d25ade2c197ca6393270e12606419872 (diff)
downloadgem5-00da08902918da13fccc3f2266b7b2f5d0080708.tar.xz
cpu: Added interface for vector reg file
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/isa.hh14
-rw-r--r--src/arch/sparc/registers.hh10
2 files changed, 24 insertions, 0 deletions
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index ded5b34ff..82fee0d00 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -202,6 +202,8 @@ class ISA : public SimObject
return RegId(CCRegClass, flattenCCIndex(regId.index()));
case MiscRegClass:
return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+ default:
+ break;
}
return regId;
}
@@ -221,6 +223,18 @@ class ISA : public SimObject
return reg;
}
+ int
+ flattenVecIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
+ flattenVecElemIndex(int reg) const
+ {
+ return reg;
+ }
+
// dummy
int
flattenCCIndex(int reg) const
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 62c876f3d..596fdf4d0 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -32,6 +32,7 @@
#ifndef __ARCH_SPARC_REGISTERS_HH__
#define __ARCH_SPARC_REGISTERS_HH__
+#include "arch/generic/vec_reg.hh"
#include "arch/sparc/generated/max_inst_regs.hh"
#include "arch/sparc/miscregs.hh"
#include "arch/sparc/sparc_traits.hh"
@@ -52,6 +53,15 @@ typedef uint32_t FloatRegBits;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
+// dummy typedefs since we don't have vector regs
+constexpr unsigned NumVecElemPerVecReg = 2;
+using VecElem = uint32_t;
+using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
+using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
+using VecRegContainer = VecReg::Container;
+// This has to be one to prevent warnings that are treated as errors
+constexpr unsigned NumVecRegs = 1;
+
typedef union
{
IntReg intReg;