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authorGeoffrey Blake <geoffrey.blake@arm.com>2012-03-09 09:59:28 -0500
committerGeoffrey Blake <geoffrey.blake@arm.com>2012-03-09 09:59:28 -0500
commit98cf57fb89b76a8ca423083d52cc647c7923fe51 (patch)
tree0376266c9e2b9381354bf86b3c7f2db4981577ea /src/arch/sparc
parent043709fdfab3b6c46f6ef95d1f642cd3c06ee20a (diff)
downloadgem5-98cf57fb89b76a8ca423083d52cc647c7923fe51.tar.xz
CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be compatible with ISAs other than ARM. This patch adds the appropriate function stubs to allow compilation.
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/tlb.cc7
-rw-r--r--src/arch/sparc/tlb.hh4
2 files changed, 11 insertions, 0 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index a6179e0f8..37f1479b0 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -841,6 +841,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+ panic("Not implemented\n");
+ return NoFault;
+}
+
Tick
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index cefa38175..89a049a8b 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -164,6 +164,10 @@ class TLB : public BaseTLB
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
+ /** Stub function for compilation support with CheckerCPU. SPARC ISA
+ * does not support the Checker model at the moment
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);