Registers: Add a registers.hh file as an ISA switched header.

This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh

12 files changed, 361 insertions, 359 deletions

diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index cfc03b718..5dcadc143 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -37,7 +37,6 @@ if env['TARGET_ISA'] == 'sparc':
     Source('isa.cc')
     Source('miscregfile.cc')
     Source('pagetable.cc')
-    Source('regfile.cc')
     Source('remote_gdb.cc')
     Source('tlb.cc')
     Source('utility.cc')
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 135bd58c3..bc9273ad3 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -40,7 +40,7 @@ output header {{
 
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/regfile.hh"
+#include "arch/sparc/registers.hh"
 #include "base/condcodes.hh"
 #include "base/misc.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 407602f90..2af624d39 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -33,7 +33,6 @@
 #define __ARCH_SPARC_ISA_TRAITS_HH__
 
 #include "arch/sparc/types.hh"
-#include "arch/sparc/max_inst_regs.hh"
 #include "arch/sparc/sparc_traits.hh"
 #include "base/types.hh"
 #include "config/full_system.hh"
@@ -48,8 +47,6 @@ namespace SparcISA
 
     //This makes sure the big endian versions of certain functions are used.
     using namespace BigEndianGuest;
-    using SparcISAInst::MaxInstSrcRegs;
-    using SparcISAInst::MaxInstDestRegs;
 
     // SPARC has a delay slot
     #define ISA_HAS_DELAY_SLOT 1
@@ -57,23 +54,6 @@ namespace SparcISA
     // SPARC NOP (sethi %(hi(0), g0)
     const MachInst NoopMachInst = 0x01000000;
 
-    // These enumerate all the registers for dependence tracking.
-    enum DependenceTags {
-        FP_Base_DepTag = 32*3+9,
-        Ctrl_Base_DepTag = FP_Base_DepTag + 64
-    };
-
-    // semantically meaningful register indices
-    const int ZeroReg = 0;      // architecturally meaningful
-    // the rest of these depend on the ABI
-    const int ReturnAddressReg = 31; // post call, precall is 15
-    const int ReturnValueReg = 8;  // Post return, 24 is pre-return.
-    const int StackPointerReg = 14;
-    const int FramePointerReg = 30;
-
-    // Some OS syscall use a second register (o1) to return a second value
-    const int SyscallPseudoReturnReg = 9;
-
     //8K. This value is implmentation specific; and should probably
     //be somewhere else.
     const int LogVMPageSize = 13;
diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc
index 28aa1e50c..b39508386 100644
--- a/src/arch/sparc/linux/process.cc
+++ b/src/arch/sparc/linux/process.cc
@@ -32,7 +32,7 @@
 
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/linux/process.hh"
-#include "arch/sparc/regfile.hh"
+#include "arch/sparc/registers.hh"
 
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 9eff7fcac..c6ba27b93 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -34,6 +34,8 @@
 
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregs.hh"
+#include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
 #include "cpu/cpuevent.hh"
 
@@ -43,125 +45,6 @@ class Checkpoint;
 
 namespace SparcISA
 {
-    enum MiscRegIndex
-    {
-        /** Ancillary State Registers */
-//        MISCREG_Y,
-//        MISCREG_CCR,
-        MISCREG_ASI,
-        MISCREG_TICK,
-        MISCREG_FPRS,
-        MISCREG_PCR,
-        MISCREG_PIC,
-        MISCREG_GSR,
-        MISCREG_SOFTINT_SET,
-        MISCREG_SOFTINT_CLR,
-        MISCREG_SOFTINT, /* 10 */
-        MISCREG_TICK_CMPR,
-        MISCREG_STICK,
-        MISCREG_STICK_CMPR,
-
-        /** Privilged Registers */
-        MISCREG_TPC,
-        MISCREG_TNPC,
-        MISCREG_TSTATE,
-        MISCREG_TT,
-        MISCREG_PRIVTICK,
-        MISCREG_TBA,
-        MISCREG_PSTATE, /* 20 */
-        MISCREG_TL,
-        MISCREG_PIL,
-        MISCREG_CWP,
-//        MISCREG_CANSAVE,
-//        MISCREG_CANRESTORE,
-//        MISCREG_CLEANWIN,
-//        MISCREG_OTHERWIN,
-//        MISCREG_WSTATE,
-        MISCREG_GL,
-
-        /** Hyper privileged registers */
-        MISCREG_HPSTATE, /* 30 */
-        MISCREG_HTSTATE,
-        MISCREG_HINTP,
-        MISCREG_HTBA,
-        MISCREG_HVER,
-        MISCREG_STRAND_STS_REG,
-        MISCREG_HSTICK_CMPR,
-
-        /** Floating Point Status Register */
-        MISCREG_FSR,
-
-        /** MMU Internal Registers */
-        MISCREG_MMU_P_CONTEXT,
-        MISCREG_MMU_S_CONTEXT, /* 40 */
-        MISCREG_MMU_PART_ID,
-        MISCREG_MMU_LSU_CTRL,
-
-        /** Scratchpad regiscers **/
-        MISCREG_SCRATCHPAD_R0, /* 60 */
-        MISCREG_SCRATCHPAD_R1,
-        MISCREG_SCRATCHPAD_R2,
-        MISCREG_SCRATCHPAD_R3,
-        MISCREG_SCRATCHPAD_R4,
-        MISCREG_SCRATCHPAD_R5,
-        MISCREG_SCRATCHPAD_R6,
-        MISCREG_SCRATCHPAD_R7,
-
-        /* CPU Queue Registers */
-        MISCREG_QUEUE_CPU_MONDO_HEAD,
-        MISCREG_QUEUE_CPU_MONDO_TAIL,
-        MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
-        MISCREG_QUEUE_DEV_MONDO_TAIL,
-        MISCREG_QUEUE_RES_ERROR_HEAD,
-        MISCREG_QUEUE_RES_ERROR_TAIL,
-        MISCREG_QUEUE_NRES_ERROR_HEAD,
-        MISCREG_QUEUE_NRES_ERROR_TAIL,
-
-        /* All the data for the TLB packed up in one register. */
-        MISCREG_TLB_DATA,
-        MISCREG_NUMMISCREGS
-    };
-
-    struct HPSTATE {
-        const static uint64_t id = 0x800;   // this impl. dependent (id) field m
-        const static uint64_t ibe = 0x400;
-        const static uint64_t red = 0x20;
-        const static uint64_t hpriv = 0x4;
-        const static uint64_t tlz = 0x1;
-    };
-
-
-    struct PSTATE {
-        const static int cle = 0x200;
-        const static int tle = 0x100;
-        const static int mm = 0xC0;
-        const static int pef = 0x10;
-        const static int am = 0x8;
-        const static int priv = 0x4;
-        const static int ie = 0x2;
-    };
-
-    struct STS {
-        const static int st_idle     = 0x00;
-        const static int st_wait     = 0x01;
-        const static int st_halt     = 0x02;
-        const static int st_run      = 0x05;
-        const static int st_spec_run = 0x07;
-        const static int st_spec_rdy = 0x13;
-        const static int st_ready    = 0x19;
-        const static int active      = 0x01;
-        const static int speculative = 0x04;
-        const static int shft_id     = 8;
-        const static int shft_fsm0   = 31;
-        const static int shft_fsm1   = 26;
-        const static int shft_fsm2   = 21;
-        const static int shft_fsm3   = 16;
-    };
-
-
-    const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
-    const int NumMiscRegs = MISCREG_NUMMISCREGS;
-
     // The control registers, broken out into fields
     class MiscRegFile
     {
diff --git a/src/arch/sparc/miscregs.hh b/src/arch/sparc/miscregs.hh
new file mode 100644
index 000000000..f7fff6ee0
--- /dev/null
+++ b/src/arch/sparc/miscregs.hh
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ *          Ali Saidi
+ */
+
+#ifndef __ARCH_SPARC_MISCREGS_HH__
+#define __ARCH_SPARC_MISCREGS_HH__
+
+#include "base/types.hh"
+
+namespace SparcISA
+{
+    enum MiscRegIndex
+    {
+        /** Ancillary State Registers */
+//        MISCREG_Y,
+//        MISCREG_CCR,
+        MISCREG_ASI,
+        MISCREG_TICK,
+        MISCREG_FPRS,
+        MISCREG_PCR,
+        MISCREG_PIC,
+        MISCREG_GSR,
+        MISCREG_SOFTINT_SET,
+        MISCREG_SOFTINT_CLR,
+        MISCREG_SOFTINT, /* 10 */
+        MISCREG_TICK_CMPR,
+        MISCREG_STICK,
+        MISCREG_STICK_CMPR,
+
+        /** Privilged Registers */
+        MISCREG_TPC,
+        MISCREG_TNPC,
+        MISCREG_TSTATE,
+        MISCREG_TT,
+        MISCREG_PRIVTICK,
+        MISCREG_TBA,
+        MISCREG_PSTATE, /* 20 */
+        MISCREG_TL,
+        MISCREG_PIL,
+        MISCREG_CWP,
+//        MISCREG_CANSAVE,
+//        MISCREG_CANRESTORE,
+//        MISCREG_CLEANWIN,
+//        MISCREG_OTHERWIN,
+//        MISCREG_WSTATE,
+        MISCREG_GL,
+
+        /** Hyper privileged registers */
+        MISCREG_HPSTATE, /* 30 */
+        MISCREG_HTSTATE,
+        MISCREG_HINTP,
+        MISCREG_HTBA,
+        MISCREG_HVER,
+        MISCREG_STRAND_STS_REG,
+        MISCREG_HSTICK_CMPR,
+
+        /** Floating Point Status Register */
+        MISCREG_FSR,
+
+        /** MMU Internal Registers */
+        MISCREG_MMU_P_CONTEXT,
+        MISCREG_MMU_S_CONTEXT, /* 40 */
+        MISCREG_MMU_PART_ID,
+        MISCREG_MMU_LSU_CTRL,
+
+        /** Scratchpad regiscers **/
+        MISCREG_SCRATCHPAD_R0, /* 60 */
+        MISCREG_SCRATCHPAD_R1,
+        MISCREG_SCRATCHPAD_R2,
+        MISCREG_SCRATCHPAD_R3,
+        MISCREG_SCRATCHPAD_R4,
+        MISCREG_SCRATCHPAD_R5,
+        MISCREG_SCRATCHPAD_R6,
+        MISCREG_SCRATCHPAD_R7,
+
+        /* CPU Queue Registers */
+        MISCREG_QUEUE_CPU_MONDO_HEAD,
+        MISCREG_QUEUE_CPU_MONDO_TAIL,
+        MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
+        MISCREG_QUEUE_DEV_MONDO_TAIL,
+        MISCREG_QUEUE_RES_ERROR_HEAD,
+        MISCREG_QUEUE_RES_ERROR_TAIL,
+        MISCREG_QUEUE_NRES_ERROR_HEAD,
+        MISCREG_QUEUE_NRES_ERROR_TAIL,
+
+        /* All the data for the TLB packed up in one register. */
+        MISCREG_TLB_DATA,
+        MISCREG_NUMMISCREGS
+    };
+
+    struct HPSTATE {
+        const static uint64_t id = 0x800;   // this impl. dependent (id) field m
+        const static uint64_t ibe = 0x400;
+        const static uint64_t red = 0x20;
+        const static uint64_t hpriv = 0x4;
+        const static uint64_t tlz = 0x1;
+    };
+
+
+    struct PSTATE {
+        const static int cle = 0x200;
+        const static int tle = 0x100;
+        const static int mm = 0xC0;
+        const static int pef = 0x10;
+        const static int am = 0x8;
+        const static int priv = 0x4;
+        const static int ie = 0x2;
+    };
+
+    struct STS {
+        const static int st_idle     = 0x00;
+        const static int st_wait     = 0x01;
+        const static int st_halt     = 0x02;
+        const static int st_run      = 0x05;
+        const static int st_spec_run = 0x07;
+        const static int st_spec_rdy = 0x13;
+        const static int st_ready    = 0x19;
+        const static int active      = 0x01;
+        const static int speculative = 0x04;
+        const static int shft_id     = 8;
+        const static int shft_fsm0   = 31;
+        const static int shft_fsm1   = 26;
+        const static int shft_fsm2   = 21;
+        const static int shft_fsm3   = 16;
+    };
+
+
+    const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
+    const int NumMiscRegs = MISCREG_NUMMISCREGS;
+}
+
+#endif
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
deleted file mode 100644
index 28ffc57aa..000000000
--- a/src/arch/sparc/regfile.cc
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- *          Ali Saidi
- */
-
-#include "arch/sparc/regfile.hh"
-#include "arch/sparc/miscregfile.hh"
-#include "cpu/thread_context.hh"
-
-using namespace SparcISA;
-
-void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-
-    uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
-
-    // Read all the trap level dependent registers and save them off
-    for(int i = 1; i <= MaxTL; i++)
-    {
-        src->setMiscRegNoEffect(MISCREG_TL, i);
-        dest->setMiscRegNoEffect(MISCREG_TL, i);
-
-        dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT));
-        dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC));
-        dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC));
-        dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE));
-    }
-
-    // Save off the traplevel
-    dest->setMiscRegNoEffect(MISCREG_TL, tl);
-    src->setMiscRegNoEffect(MISCREG_TL, tl);
-
-
-    // ASRs
-//    dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y));
-//    dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR));
-    dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI));
-    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
-    dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS));
-    dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT));
-    dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
-    dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK));
-    dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
-
-    // Priv Registers
-    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
-    dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA));
-    dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE));
-    dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL));
-    dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP));
-//    dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE));
-//    dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE));
-//    dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN));
-//    dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN));
-//    dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE));
-    dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
-
-    // Hyperprivilged registers
-    dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE));
-    dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP));
-    dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA));
-    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
-            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
-    dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
-            src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
-
-    // FSR
-    dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR));
-
-    //Strand Status Register
-    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
-            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
-
-    // MMU Registers
-    dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
-            src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
-    dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
-            src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
-    dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
-            src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
-    dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
-            src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
-
-    // Scratchpad Registers
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
-    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
-            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
-
-    // Queue Registers
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
-    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
-            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
-}
-
-void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    //First loop through the integer registers.
-    int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
-    int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
-    //Globals
-    for (int x = 0; x < MaxGL; ++x) {
-        src->setMiscRegNoEffect(MISCREG_GL, x);
-        dest->setMiscRegNoEffect(MISCREG_GL, x);
-        // Skip %g0 which is always zero.
-        for (int y = 1; y < 8; y++)
-            dest->setIntReg(y, src->readIntReg(y));
-    }
-    //Locals and ins. Outs are all also ins.
-    for (int x = 0; x < NWindows; ++x) {
-         src->setMiscRegNoEffect(MISCREG_CWP, x);
-         dest->setMiscRegNoEffect(MISCREG_CWP, x);
-         for (int y = 16; y < 32; y++)
-             dest->setIntReg(y, src->readIntReg(y));
-    }
-    //Microcode reg and pseudo int regs (misc regs in the integer regfile).
-    for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
-        dest->setIntReg(y, src->readIntReg(y));
-
-    //Restore src's GL, CWP
-    src->setMiscRegNoEffect(MISCREG_GL, old_gl);
-    src->setMiscRegNoEffect(MISCREG_CWP, old_cwp);
-
-
-    // Then loop through the floating point registers.
-    for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
-        dest->setFloatRegBits(i, src->readFloatRegBits(i));
-    }
-
-    // Copy misc. registers
-    copyMiscRegs(src, dest);
-
-
-    // Lastly copy PC/NPC
-    dest->setPC(src->readPC());
-    dest->setNextPC(src->readNextPC());
-    dest->setNextNPC(src->readNextNPC());
-}
-
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/registers.hh
index 28885271f..639b7a487 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/registers.hh
@@ -29,27 +29,51 @@
  *          Ali Saidi
  */
 
-#ifndef __ARCH_SPARC_REGFILE_HH__
-#define __ARCH_SPARC_REGFILE_HH__
+#ifndef __ARCH_SPARC_REGISTERS_HH__
+#define __ARCH_SPARC_REGISTERS_HH__
 
-#include <iostream>
-#include <string>
-
-#include "arch/sparc/miscregfile.hh"
+#include "arch/sparc/max_inst_regs.hh"
+#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/sparc_traits.hh"
-
-class Checkpoint;
-class EventManager;
-class ThreadContext;
+#include "base/types.hh"
 
 namespace SparcISA
 {
-    const int NumIntArchRegs = 32;
-    const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
+    using SparcISAInst::MaxInstSrcRegs;
+    using SparcISAInst::MaxInstDestRegs;
+
+    typedef uint64_t IntReg;
+    typedef uint64_t MiscReg;
+    typedef float FloatReg;
+    typedef uint32_t FloatRegBits;
+    typedef union
+    {
+        IntReg intReg;
+        FloatReg fpreg;
+        MiscReg ctrlreg;
+    } AnyReg;
 
-    void copyRegs(ThreadContext *src, ThreadContext *dest);
+    typedef uint16_t RegIndex;
 
-    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+    // These enumerate all the registers for dependence tracking.
+    enum DependenceTags {
+        FP_Base_DepTag = 32*3+9,
+        Ctrl_Base_DepTag = FP_Base_DepTag + 64
+    };
+
+    // semantically meaningful register indices
+    const int ZeroReg = 0;      // architecturally meaningful
+    // the rest of these depend on the ABI
+    const int ReturnAddressReg = 31; // post call, precall is 15
+    const int ReturnValueReg = 8;  // Post return, 24 is pre-return.
+    const int StackPointerReg = 14;
+    const int FramePointerReg = 30;
+
+    // Some OS syscall use a second register (o1) to return a second value
+    const int SyscallPseudoReturnReg = 9;
+
+    const int NumIntArchRegs = 32;
+    const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
 
 } // namespace SparcISA
 
diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc
index 22924736b..eafb488df 100644
--- a/src/arch/sparc/solaris/process.cc
+++ b/src/arch/sparc/solaris/process.cc
@@ -30,7 +30,7 @@
 
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/solaris/process.hh"
-#include "arch/sparc/regfile.hh"
+#include "arch/sparc/registers.hh"
 
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh
index c7ece9dfa..70558ec6d 100644
--- a/src/arch/sparc/types.hh
+++ b/src/arch/sparc/types.hh
@@ -39,19 +39,7 @@ namespace SparcISA
     typedef uint32_t MachInst;
     typedef uint64_t ExtMachInst;
 
-    typedef uint64_t IntReg;
     typedef Twin64_t LargestRead;
-    typedef uint64_t MiscReg;
-    typedef float FloatReg;
-    typedef uint32_t FloatRegBits;
-    typedef union
-    {
-        IntReg intReg;
-        FloatReg fpreg;
-        MiscReg ctrlreg;
-    } AnyReg;
-
-    typedef uint16_t RegIndex;
 
     struct CoreSpecific {
         int core_type;
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index d4cc286e6..9c9b833fe 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -61,4 +61,159 @@ uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
     M5_DUMMY_RETURN
 #endif
 }
+
+void
+copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+
+    uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
+
+    // Read all the trap level dependent registers and save them off
+    for(int i = 1; i <= MaxTL; i++)
+    {
+        src->setMiscRegNoEffect(MISCREG_TL, i);
+        dest->setMiscRegNoEffect(MISCREG_TL, i);
+
+        dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT));
+        dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC));
+        dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC));
+        dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE));
+    }
+
+    // Save off the traplevel
+    dest->setMiscRegNoEffect(MISCREG_TL, tl);
+    src->setMiscRegNoEffect(MISCREG_TL, tl);
+
+
+    // ASRs
+//    dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y));
+//    dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR));
+    dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI));
+    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
+    dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS));
+    dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT));
+    dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
+    dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK));
+    dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
+
+    // Priv Registers
+    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
+    dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA));
+    dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE));
+    dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL));
+    dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP));
+//    dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE));
+//    dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE));
+//    dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN));
+//    dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN));
+//    dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE));
+    dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
+
+    // Hyperprivilged registers
+    dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE));
+    dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP));
+    dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA));
+    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
+            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
+    dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
+            src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
+
+    // FSR
+    dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR));
+
+    //Strand Status Register
+    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
+            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
+
+    // MMU Registers
+    dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
+            src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
+    dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
+            src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
+    dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
+            src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
+    dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
+            src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
+
+    // Scratchpad Registers
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
+
+    // Queue Registers
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
+}
+
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+    //First loop through the integer registers.
+    int old_gl = src->readMiscRegNoEffect(MISCREG_GL);
+    int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP);
+    //Globals
+    for (int x = 0; x < MaxGL; ++x) {
+        src->setMiscRegNoEffect(MISCREG_GL, x);
+        dest->setMiscRegNoEffect(MISCREG_GL, x);
+        // Skip %g0 which is always zero.
+        for (int y = 1; y < 8; y++)
+            dest->setIntReg(y, src->readIntReg(y));
+    }
+    //Locals and ins. Outs are all also ins.
+    for (int x = 0; x < NWindows; ++x) {
+         src->setMiscRegNoEffect(MISCREG_CWP, x);
+         dest->setMiscRegNoEffect(MISCREG_CWP, x);
+         for (int y = 16; y < 32; y++)
+             dest->setIntReg(y, src->readIntReg(y));
+    }
+    //Microcode reg and pseudo int regs (misc regs in the integer regfile).
+    for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
+        dest->setIntReg(y, src->readIntReg(y));
+
+    //Restore src's GL, CWP
+    src->setMiscRegNoEffect(MISCREG_GL, old_gl);
+    src->setMiscRegNoEffect(MISCREG_CWP, old_cwp);
+
+
+    // Then loop through the floating point registers.
+    for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) {
+        dest->setFloatRegBits(i, src->readFloatRegBits(i));
+    }
+
+    // Copy misc. registers
+    copyMiscRegs(src, dest);
+
+
+    // Lastly copy PC/NPC
+    dest->setPC(src->readPC());
+    dest->setNextPC(src->readNextPC());
+    dest->setNextNPC(src->readNextNPC());
+}
 } //namespace SPARC_ISA
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index c0c3756f5..551570723 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -116,6 +116,10 @@ namespace SparcISA
 #endif
     }
 
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
 } // namespace SparcISA
 
 #endif