diff options
| author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2012-11-02 11:32:01 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2012-11-02 11:32:01 -0500 |
| commit | c0ab52799ca4ebd0a51363cfedd0658e6d79b842 (patch) | |
| tree | afdf65e4593c64bbc1d5b511aacbaf0fa4b558ad /src/arch/sparc | |
| parent | 044a6525876efc61838dffa89ac52425d510b754 (diff) | |
| download | gem5-c0ab52799ca4ebd0a51363cfedd0658e6d79b842.tar.xz | |
sim: Include object header files in SWIG interfaces
When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.
This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
Diffstat (limited to 'src/arch/sparc')
| -rw-r--r-- | src/arch/sparc/SparcInterrupts.py | 1 | ||||
| -rw-r--r-- | src/arch/sparc/SparcNativeTrace.py | 1 | ||||
| -rw-r--r-- | src/arch/sparc/SparcSystem.py | 1 | ||||
| -rw-r--r-- | src/arch/sparc/SparcTLB.py | 1 |
4 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/sparc/SparcInterrupts.py b/src/arch/sparc/SparcInterrupts.py index 2cc964c2d..c11176164 100644 --- a/src/arch/sparc/SparcInterrupts.py +++ b/src/arch/sparc/SparcInterrupts.py @@ -31,3 +31,4 @@ from m5.SimObject import SimObject class SparcInterrupts(SimObject): type = 'SparcInterrupts' cxx_class = 'SparcISA::Interrupts' + cxx_header = 'arch/sparc/interrupts.hh' diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py index 0a92764ef..cdc34b541 100644 --- a/src/arch/sparc/SparcNativeTrace.py +++ b/src/arch/sparc/SparcNativeTrace.py @@ -33,3 +33,4 @@ from NativeTrace import NativeTrace class SparcNativeTrace(NativeTrace): type = 'SparcNativeTrace' cxx_class = 'Trace::SparcNativeTrace' + cxx_header = 'arch/sparc/nativetrace.hh' diff --git a/src/arch/sparc/SparcSystem.py b/src/arch/sparc/SparcSystem.py index b0fddf311..9d8be5d06 100644 --- a/src/arch/sparc/SparcSystem.py +++ b/src/arch/sparc/SparcSystem.py @@ -33,6 +33,7 @@ from System import System class SparcSystem(System): type = 'SparcSystem' + cxx_header = 'arch/sparc/system.hh' _rom_base = 0xfff0000000 _nvram_base = 0x1f11000000 _hypervisor_desc_base = 0x1f12080000 diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py index 0c3fdc7fb..219f6842a 100644 --- a/src/arch/sparc/SparcTLB.py +++ b/src/arch/sparc/SparcTLB.py @@ -34,4 +34,5 @@ from BaseTLB import BaseTLB class SparcTLB(BaseTLB): type = 'SparcTLB' cxx_class = 'SparcISA::TLB' + cxx_header = 'arch/sparc/tlb.hh' size = Param.Int(64, "TLB size") |