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authorGabe Black <gblack@eecs.umich.edu>2008-10-12 08:24:09 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-12 08:24:09 -0700
commitc4f1cc3b482311f878be44259125c9a5b90c0569 (patch)
tree45e108b762d6876c150d3f56171c005e3474405a /src/arch/sparc
parent0c3848732ee33cf14a80129f6cf7ee84d51c8bfb (diff)
downloadgem5-c4f1cc3b482311f878be44259125c9a5b90c0569.tar.xz
CPU: Eliminate the get_vec function.
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/tlb.cc33
1 files changed, 24 insertions, 9 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 125ceba69..61f0985db 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1008,12 +1008,22 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
itb->cx_config));
break;
case ASI_SWVR_INTR_RECEIVE:
- pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
+ {
+ SparcISA::Interrupts * interrupts =
+ dynamic_cast<SparcISA::Interrupts *>(
+ tc->getCpuPtr()->getInterruptController());
+ pkt->set(interrupts->get_vec(IT_INT_VEC));
+ }
break;
case ASI_SWVR_UDB_INTR_R:
- temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
- tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
- pkt->set(temp);
+ {
+ SparcISA::Interrupts * interrupts =
+ dynamic_cast<SparcISA::Interrupts *>(
+ tc->getCpuPtr()->getInterruptController());
+ temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
+ tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
+ pkt->set(temp);
+ }
break;
default:
doMmuReadError:
@@ -1252,11 +1262,16 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
}
break;
case ASI_SWVR_INTR_RECEIVE:
- int msb;
- // clear all the interrupts that aren't set in the write
- while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) {
- msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data);
- tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
+ {
+ int msb;
+ // clear all the interrupts that aren't set in the write
+ SparcISA::Interrupts * interrupts =
+ dynamic_cast<SparcISA::Interrupts *>(
+ tc->getCpuPtr()->getInterruptController());
+ while(interrupts->get_vec(IT_INT_VEC) & data) {
+ msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
+ tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
+ }
}
break;
case ASI_SWVR_UDB_INTR_W: